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In our previous work, the reduced code based method has been proposed to significantly reduce the linearity test time of a pipelined ADC. The digital error correction (DEC) technique is extensively employed in a pipelined ADC. A pipelined ADC with this technique can tolerate large comparator offset without degrading the ADC linearity. However, in this paper, we find that comparator offsets would cause...
This paper presents a leakage characterization technique for switched capacitor (SC) integrators. It is a low-cost on-chip solution because (1) the test stimulus is a DC voltage whose exact value is not important, and (2) the output response digitizer is simply a comparator. Simulation results show that integrator leakage can be accurately characterized even in the presence of noise and comparator...
Several low-power, single- and multi-stage ΔΣ modulators were designed in a 1.2-V 0.13-nm UMC CMOS process. The distinguishing feature of these modulators is the elimination of operational amplifiers (opamps) in the loop filters and their replacement by comparators with current sources at their outputs. These so-called comparator-based switched-capacitor (CBSC) circuits offer several advantages over...
In this paper, we present a histogram-based two-phase calibration technique for capacitor mismatch and comparator offset of 1-bit/stage pipelined Analog-to-Digital Converters (ADCs). In the first phase, it calibrates the missing decision levels by capacitor resizing. Unlike previous works which require large capacitor arrays, only few switches are added to the circuit. The second phase performs missing...
In this paper, we present an efficient calibration technique for 1-bit/stage pipelined analog-to-digital converters (ADCs). The proposed technique calibrates capacitor mismatch and comparator offset induced non-ideal ADC output behavior; it is a two-phase calibration scheme that relies on linear histogram testing to collect the required information. In the first phase, it calibrates the missing-decision-level...
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