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This paper presents a self-testing and calibration method for the embedded successive approximation register (SAR) analog-to-digital converter (ADC). We first propose a low cost design-for-test (DfT) technique which tests a SAR ADC by characterizing its digital-to-analog converter (DAC) capacitor array. Utilizing DAC major carrier transition testing, the required analog measurement range is just 4...
In this paper, we propose a novel versatile engine for behavioral or transistor-level design verification of data converters. This tool is dedicated to IC designers to verify static performance of the converters during their design. It is based on advanced Servo-Loop method presented in and extended by features such as innovative DAC testing method (connecting ADC and DAC testing into one versatile...
The ideal goal of semiconductor quality assurance is to provide zero defective parts to the customer. In practice this goal is limited by test quality and test cost due to expensive ATE resources. It is typically not feasible to provide zero Defective Parts per Million (DPPM) for majority of applications due to the high costs of testing involved. Comprehensive functional tests to find all detectable...
In our previous work, the reduced code based method has been proposed to significantly reduce the linearity test time of a pipelined ADC. The digital error correction (DEC) technique is extensively employed in a pipelined ADC. A pipelined ADC with this technique can tolerate large comparator offset without degrading the ADC linearity. However, in this paper, we find that comparator offsets would cause...
This paper presents a leakage characterization technique for switched capacitor (SC) integrators. It is a low-cost on-chip solution because (1) the test stimulus is a DC voltage whose exact value is not important, and (2) the output response digitizer is simply a comparator. Simulation results show that integrator leakage can be accurately characterized even in the presence of noise and comparator...
This paper presents an intelligent secondary battery test system based on a 24-bit high-resolution ADC ADS1211. We adopt ultra-high precision voltage reference AD780 and 24-bit ADC ADS1211 to ensure high-precision measurement. The system utilizes a micro-controller to intelligently set the parameters of channel state control circuit, switch charge-discharge mode, switch voltage and current feedback,...
The cost of testing mixed signal circuitry with conventional analog-stimulus is significantly higher than digital circuitry due to higher cost automatic test equipment (ATE) required for generation of analog stimulus. Multiple variants of low cost testers have been developed for digital testing which rely on relaxed timing, power or tester channel requirements to lower hardware cost. Systems containing...
In this paper, we present a histogram-based two-phase calibration technique for capacitor mismatch and comparator offset of 1-bit/stage pipelined Analog-to-Digital Converters (ADCs). In the first phase, it calibrates the missing decision levels by capacitor resizing. Unlike previous works which require large capacitor arrays, only few switches are added to the circuit. The second phase performs missing...
In this work, a characteristic observation method is proposed to reduce the test time for the INL and DNL testing of a pipelined A/D converter. The symmetrical and specific regular rules are concluded by analyzing the characteristic of a pipelined ADC. As a result, based on the specific rules, only a few code bin widths of specific codes should be measured to accomplish the accurate full-code INL/DNL...
In this paper, we have proposed a new high precision ramp waveform generator for low cost ADC test. With proposed test method combined with histogram analysis, an ADC can be easily tested on general digital testers. In our approach, we combine a traditional ramp generator with proper gain of operational amplifier (OPA) for ADC test. This new ramp generator structure can reduce the effect of output...
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash...
In this paper, we present an efficient calibration technique for 1-bit/stage pipelined analog-to-digital converters (ADCs). The proposed technique calibrates capacitor mismatch and comparator offset induced non-ideal ADC output behavior; it is a two-phase calibration scheme that relies on linear histogram testing to collect the required information. In the first phase, it calibrates the missing-decision-level...
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