The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Mitigation of radiation effects is one of the major problems for space-borne computing platforms. The presented work proposes an approach for building reliable, hardware fault adaptive stream processing platforms for space applications. The proposed concept is based on architecture-to-fault adaptation by run-time hardware reconfiguration. The concept assumes representation of system components in...
The wormhole attack is a severe attack in Wireless Mesh Networks (WMNs). It involves two or more wormhole endpoints colluding to capture traffic from one place in the network and replay it to another faraway place through a secret tunnel, so as to distort network routing. It may lead to even more serious threats such as packet dropping and denial of service (DoS). Although a lot of works have been...
Barrier synchronization is a key programming primitive for shared memory embedded MPSoCs. As the core count increases, software implementations cannot provide the needed performance and scalability, thus making hardware acceleration critical. In this paper we describe an interconnect extension implemented with standard cells and with a mainstream industrial toolflow. We show that the area overhead...
Reliabilities for the technologies of position detection mean the measurement errors in the position detection. Presently, there are many different technologies used in position detection. But, as signal receiver operating in different locations are used to detect precise positions of objects located at long distances, it is hard to know when a object's or user's-terminal devices send a signal[1]...
Time-based localization protocols allow a trusted set of nodes called verifiers to determine the location of a node that is not trusted (and possibly malicious), called the prover. Existing literature on secure localization protocols is concerned with defending against various attack models by restructuring the message exchanges and/or cryptographic issues related to the challenge-response dialog...
Time synchronization is the necessary technique to implement automation system in smart substations. It provides the accuracy time stamp mark used for data acquisition and used to analyze and deal with the power system fault. As a type of clock synchronization used in network with high precision, IEEE1588 is widespread applied recently in smart substations. This paper analyzes the reason of clock...
The research deals with the synchronization of the signals to trigger Measurement Instruments (MIs) cooperating in the distributed measurement system. Due to the hardware and software architecture of the Trigger Generator (TrG) common available (es. PC), the signal is received by MIs with random delay. Solution based on Embedded Synchronizing Hardware (ESH) was proposed to ensure synchronization accuracy...
The paper introduces a novel software defined radio system named Sora and analyzes its system architecture. For the special characteristics of radio channel in high speed scenario,we research a novel scheme based on wireless cell network WCDMA for channel sounding in High-Speed Railway. According to developing an application that simulates the transmition and reception of WCDMA siganl by User-Mode...
Simulation-based verification is a widely-spread approach to ensure functional correctness of hardware designs [1,2]. It is usually done by co-simulating a design under verification with an independently created reference model and checking conformance of their reactions. To reduce verification expenses, abstract models are commonly used (they are simpler, less error-prone and more reusable). Design...
HW/SW Codesign [4] is a strategy to develop highly optimized systems composed of both electronics hardware and software. Examples are smartphones, consumer electronics or embedded systems. The challenge is to achieve an optimized split by partitioning the system components into hardware and software and to achieve the best project execution time (and cost) by developing both hardware and software...
Industrial Ethernet-based motor drives offer many advantages for motion applications. This paper presents the implementation and analysis of a motor drive with the EtherCAT, an open real-time Ethernet standard, for high-precision motion systems. Considering the characteristics of the multitasked software and the network interface, we analyze the delay in actuating the motor in response to a command...
IEEE1588 is a Precise Time Protocol (PTP), which is of potentially wide application in control and measurement networks. Stamping PTP messages accurately in physical layer taking advantage of hardware circuits, it is one of important key technologies to achieve the object of high precision time synchronization of IEEE1588. This paper analyzes the content of IEEE1588 standard in detail, and proposes...
Evaluation of Wireless Sensor Networks is difficult. Due to lack of standard implementations, stringent time requirements and security enabled communications evaluation of WirelessHART networks is challenging. This makes it very hard to compare, evaluate and test WirelessHART networks even controlled environments. We propose a hybrid simulation framework that is tailored for the WirelessHART protocol...
The synchronization is a key point in measurement and control systems, which use technologies such as network communication, local computing and distributed objects. Modern industrial application is demanding the synchronization for higher precision, this paper analyzes a variety of synchronous time synchronization protocols used in the current industrial Ethernet applications, mean-while explains...
This paper investigates the potential of emerging asynchronous quasi delay insensitive (a-QDI) logic devices for the realization of high-speed low-power 2D infinite impulse response digital beam filters. Recently proposed raster-scanned hardware architectures based on direct-form I and wave-digital realization are extended to clock-free asynchronous logic using state-of-the-art asynchronous field...
The specifications of the control units driving embedded systems often involve temporal properties. We aim at certifying them statically using the Abstract Interpretation framework and introduce several Abstract Domains dedicated to proving such temporal properties. This work defines the specificity of such domains, that we call Temporal Abstract Domains. We introduce a continuous-time abstraction,...
Transactional Memories (TM) have attracted much interest as an alternative to lock-based synchronization in shared-memory multiprocessors. Considering the use of TM on an embedded, NoC-based MPSoC, this work evaluates a LogTM implementation. It is shown that the time an aborted transaction waits before restarting its execution (the backoff delay) can seriously affect the overall performance and energy...
Multicore has become a trend on server and client computers in recent years. Parallelization is one way to fully utilize the computing power provided by multicore architectures. Most applications of interest have complex data and control dependency, which make traditional parallelization techniques, such as DOALL and DOACROSS, inapplicable. Decoupled Software Pipelining (DSWP), a new parallelization...
This paper proposes a new theory of adder and its basic structure. The new adder is an asynchronous adder whose basic unit is half adder, called Parallel Feedback Carry Adder (PFCA) as its carry mode is parallel feedback. In theory, compared to the adders (e.g. RCA, CLA, CSeA) based on full adder, PFCA is faster in speed and smaller in area. A CMOS gate implementation is proposed to verify the new...
Clock skew minimization has been an important design constraint. However, due to the complexity of Process, Voltage, and Temperature (PVT) variations, the minimization of clock skew has faced a great challenge. To overcome the influence of PVT variations, several previous works proposed Post Silicon Tuning (PST) architecture to dynamically balance the skew of a clock tree. In the PST architecture,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.