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An adjustable pulse module with FPGA-based 0.1 ns resolution is designed, which has the function of simultaneously generating multi-channel pulse. Various pulses time delay can be adjusted each other. Therefore it can improve the small target RCS (radar cross section) test accuracy under the complex environment. At present, the technology is successfully applied to a RCS tester.
Mitigation of radiation effects is one of the major problems for space-borne computing platforms. The presented work proposes an approach for building reliable, hardware fault adaptive stream processing platforms for space applications. The proposed concept is based on architecture-to-fault adaptation by run-time hardware reconfiguration. The concept assumes representation of system components in...
The design and implementation on an FPGA of a correlation system for the American and Russian Global Positioning Systems (GPS and GLONASS) receivers are presented in this paper. This system permits processing the received signal asynchronously with the data-bits. Typically, in GPS and GLONASS receivers, correlation channels receive the samples in intermediate frequency signal, process them through...
In this paper, we present a design of a USB 2.0 interface for ARM7TDM-S system. The whole system is implemented on a Virtex-5 FPGA and uses a separate external USB 2.0 transceiver hardware for signaling requirements. The design is coded in Verilog HDL. The project utilizes the Xilinx ISE Design Suite workflow. The system supports USB communication from the ARM7 system on the FPGA to the USB Host PC,...
A hardware-based solution of precise time synchronization over Ethernet was proposed for Networked Control System (NCS). Using Field-programmable Gate Array (FPGA), hardware-based solution was designed for implementing time synchronization protocol defined in IEEE 1588. Timestamp capture, oscillator frequency compensation, time synchronization and etc., were all coded with Very High Speed Integrated...
This paper presents the experimental synchronization of multiple time delay systems which are implemented on a Field Programmable Gate Array (FPGA). The obtained results verify the correctness and the feasibility of theoretical synchronization. Moreover, the digital approach here could be applied to arbitrary multi-delay feedback systems to realize secure chaotic communication.
IEEE1588 is a Precise Time Protocol (PTP), which is of potentially wide application in control and measurement networks. Stamping PTP messages accurately in physical layer taking advantage of hardware circuits, it is one of important key technologies to achieve the object of high precision time synchronization of IEEE1588. This paper analyzes the content of IEEE1588 standard in detail, and proposes...
Nowadays the need for dealing with ultra-high speed Analog to Digital Converter (ADC) is becoming more and more common, from Telecommunications to Precise Instrumentation, every application is increasing the analog to digital interface data rate. The ultra-high sampling rate of the ADCs demands the use of advanced acquisition techniques as well as the latest technology available. The utilization of...
In this paper factors affecting accuracy of time synchronization in EPON are analysed and the scheme of time synchronization in EPON based on IEEE1588v2 protocol is designed and implemented by FPGA. Experimental result shows that the scheme is feasible and good time synchronization accuracy about 20 nanoseconds can be reached.
As circuits grow larger and faster, electromagnetic interference (EMI) plays an increasingly important role in equipment design. To deal with EMI and make designs comply with related standards, engineers have several techniques at their disposal, some applicable at the design phase, others at the implementation phase. This paper deals with asynchronous systems as a means of reducing EMI. Lower magnetic...
This article introduced a design principles and implementation method of a high resolution programmable digital delay generator. It described the system's composition in hardware and software view. This system is composed of deserializer MAX3885, high-speed clock generator AD9517-1, DDR2 SDRAM, serializer and USB2.0 Controller. Paper described FPGA software design methods includes DDR2 SDRAM controller...
Using IEEE 1588 for highly accurate clock synchronization between nodes of a distributed system has become a widely accepted approach. IEEE 802.3/Ethernet is frequently utilized as communication layer to exchange the Precision Time Protocol (PTP) messages specified in the IEEE 1588 standard. 10/100/1000 MBit Ethernet communication is commonly used by now. In contrast, fiber optics based 10 GBit Ethernet...
This paper presents an accurate and simple delay measurement method based on Xilinx's Digital Clock Managers. Particularly, variable phase shift is the modules' capability exploited in our approach. This method enables the implementation of a time-to-digital converter that achieves a resolution of 200ps on a Xilinx's Virtex or Spartan-3 FPGA without requiring manual placement & routing, nor an...
SPI is one of the most commonly used serial protocols for both inter-chip and intra-chip low/medium speed data-stream transfers. In conformity with design-reuse methodology, this paper introduces high-quality SPI Master/Slave IPs that incorporate all necessary features required by modern ASIC/SoC applications. Based upon Motorola's SPI-bus specifications, version V03.06, release February 2003, the...
The purpose of this paper is to present a new method and structure for the automatic configuration of a digital system to unknown delays in synchronous input data channels. The method makes possible to restore synchronism in node-to-node communication. Synchronism may be lost due to different delays introduced by the various communication channels. The proposed method allows differences in the channel...
Time based localisation methods like GPS are widely used for outdoor navigation, whereas indoor navigation is typically performed only on a cell-basis or based on the Received Signal Strength Indicator. Since RSSI is not able to fulfil all current requirements, Time of Arrival and Time Difference of Arrival based approaches have recently gained focus. As time based localisation has high demands on...
An asynchronism problem between High-Speed DAC Chips in some multi-channel systems is analyzed. And, a method to solve this problem is proposed: Finding out the difference between clocks of each DAC, then compensating through data based on the difference in order to synchronize them. At the end, a diagram is proposed to solve the problem with this method in FPGA.
The construction and design process of a high-resolution time-interval measuring system implemented in a SRAM-based FPGA device is discussed in this paper. The TDC can increase the precision on the measurement by interpolating time within the system clock cycle. A two step phase interpolation has been constructed, one based on the phase information delivered by the VIRTEX-5 Digital Clock Manager (DCM)...
A methodology for implementing GALS design in conventional FPGAs using existing tools is presented. The goals were to define the minimal set of basic asynchronous components, to examine the methodology of their implementation and to establish the design constraints and limitations of such circuits. Simulation results confirm that GALS designs implemented using the Look-Up Table or the Flip-Flop with...
For high precision acquiring of low-frequency vibration signal in large-scale area, a data acquisition system employing serial chain structure is implemented. Four data acquisition channels which are based on 24-bit sigma-delta modulator CS5372 and digital filter CS5376A are implemented on each acquisition node. Excellent analog performance with circuit noise less than 1.6 muV and total harmonic distortion...
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