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We present a fully programmable layered LDPC decoder architecture together with an optimum mapping and scheduling algorithm. In contrast to other designs proposed in the literature, we use one-phase message passing. This allows for the first time the design of a fully programmable layered decoder. The proposed mapping and scheduling algorithm exploits the full parallelism of the architecture at any...
Pipelined layered decoder (PLD) of quasi-cyclic low-density parity-check (QC-LDPC) codes is one of most popular high-throughput decoder in modern communication systems. However, the traditional QC-LDPC codes are not suitable for PLD and lead to memory access conflict problems (MACPs) that reduce the throughput of PLD. Therefore, an efficient layered block progressive edge-growth (EL-BPEG) algorithm...
We present a doubly parallelized layered quasi-cyclic low-density parity-check decoder for the emerging IEEE 802.11ad multigigabit wireless standard. The decoding algorithm is equivalent to a non-parallelized layered decoder and, thus, retains its favorable convergence characteristics, which are known to be superior to those of flooding schedule based decoders. The proposed architecture was synthesized...
In this paper, we present a flexible high-throughput LDPC decoder architecture that can support different code rates and block sizes in wireless applications such as IEEE 802.11n, IEEE 802.16e, and IEEE 802.15.3c standards. Several flexible LDPC decoders have been presented in the literature but their throughput (less than 640 Mbps) is limited due to block-serial scheduling of the decoding computations...
Three families of architectures for LDPC decoding are presented in this paper, aiming at the reduction of the interconnection complexity dominant in an LDPC decoder. The proposed architectures explore tradeoffs between the interconnection complexity, delay, and decoding performance. A graph-based technique is introduced that allows the formation of groups of calculations, such that inter-group communication...
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