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This paper presents an efficient architecture of finding the first two minimum values for row operation in LDPC decoding. Given a set of numbers X, efficient algorithm and its corresponding hardware implementation for finding the first minimum value, min_1st, second minimum value, min_2nd and the position of min_1st are greatly needed in LDPC decoder design. The design is based on sorting-based approach...
A novel architecture for the LDPC decoder with Chinese DTTB standard is presented in this paper. Two kinds of schemes to do the minimizing operations in the horizontal process of min-sum algorithm are compared, and then a foldable horizontal process unit is developed to support the splitting-matrix architecture, which is a reuse architecture based on check matrix splitting to increase the resource...
High-throughput design approaches for quasi-cyclic (QC) low-density parity-check (LDPC) decoders are presented in this paper. Three novel schemes for the horizontal process in min-sum algorithm and its revisions are derived to reduce design and implementation complexity. The schemes can be directly applied for variant QC codes and easily pipelined to increase the operating frequency of the decoder...
In this paper, a matrix permutation scheme is proposed to convert a generic QC-LDPC code to a shift-structured LDPC code. Thus, efficient VLSI architectures can be developed to achieve very high decoding throughput with low hardware complexity. Furthermore, novel implementation schemes for min-sum algorithm based column-layered decoding are presented. The proposed approaches provide very efficient...
In this paper, we present a novel high-speed dual-core programmable decoder architecture for LDPC convolutional codes and their tail-biting versions. This architecture uses a modified Min-Sum algorithm and enables the decoding of a multitude of codes with different node degree distributions, rates and block lengths. We show how the parallelization concepts are derived using the properties of the bipartite...
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