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This article proposes an original methodology for the fast prototyping of image processing on a generic MP-SoC (Multi-Processors System on Chip) architecture. To define a processors network adapted to a particular application is critical and design-time consuming in order to achieve high-performance customized solutions. The effectiveness of such approaches largely depends on the availability of an...
This article proposes an original design flow for the fast prototyping of image processing on a MP-SoC (MultiProcessors System on Chip) architecture. Developing processors network systems tailored to a particular application domain is critical and design-time consuming in order to achieve high-performance customized solutions. The effectiveness of such approaches largely depends on the availability...
Embedded systems designers frequently avoid using floating-point computation because it is too costly to include a floating-point unit (FPU) in an embedded processor. However, the performance of software floating-point libraries can be lacking. Therefore we propose a fractured floating point unit (FFPU)-a hybrid solution using a mix of custom hardware instructions and software code. An FFPU is designed...
This paper presents a methodology for high-level power modeling of cell-based processors. A flexible power model library, which can automatically generate detailed power data for actual circuits of each part of given processor, is developed and annotated dynamically for architecture-level power simulator. According to this method, the dynamic power, leakage power and even area and cell counts can...
This paper explores the usefulness of the Sony PlayStation 3reg(PS3) for medical image processing. Medical image processing often entails dealing with a large number of high resolution images, requiring a large amount of computational power to process. The PS3 is powered by the cell broadband engine, a microprocessor created by IBM, capable of rapid numeric computation with low power requirements...
In the paper, we investigate the memory access technology on cell broadband engine architecture (CBEA), and develop a profiling infrastructure for memory management on the architecture. By registering the dynamic memory allocation and providing details of trace of memory access, the infrastructure provides the data partition information automatically which alleviates the burdens of programmer and...
Computer architecture science evolves continuously. This work describes a methodology to teach a system which is integrated by several processors in just one chip. The description of how to implement a biprocessor system within an FPGA is proposed. Thus, the student will simultaneously acquire advanced knowledge on microprocessors, focusing on the operational behavior and structure of a biprocessor...
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