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Demand for system-on-chip solutions has increased the interest in low drop-out (LDO) voltage regulators which do not require a bulky off-chip capacitor to achieve stability, also called capacitor-less LDO (CL-LDO) regulators. Several architectures have been proposed; however comparing these reported architectures proves difficult, as each has a distinct process technology and specifications. This...
This paper presents the design and experimental characterization of two output-capacitor-free adaptively biased low-dropout regulators (AB LDRs) for system-on-chip applications. The low-voltage high-precision AB LDRs adopt Miller compensation and Q-reduction technique to achieve high stability over a wide load current range, without relying on a large off-chip capacitor. The first implementation of...
An off-chip capacitor-free CMOS low-dropout voltage regulator (LDO) for full on chip power management solution is presented. The proposed structure based on modified nested Miller compensation and transient enhancement network provides both fast load transient response and full load stability. For a pulsed load current between 0.5 mA and 50 mA, it is able to recover within ~3.5 mus and a less than...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
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