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The Flash technology is the most popular non-volatile memory technology. In this paper, we present the ability of a SPICE-like model of the ATMEL TSTAC™ eFlash technology to guide the design and test phases. This model is composed of two layers: a functional layer representing the Floating Gate (FG) and a programming layer able to determine the channel voltage level controlling the Fowler-Nordheim...
In mobile systems, the demand for the energy saving continues to require a low power memory sub-system. During the last decade, the floating-gate flash mem ory has been an indispensable low power memory solution. However, NOR flash memory has begun to show difficulties in scaling due to the device's reliability and yield issues. Over the past few years, phase-change random access memory (PRAM) has...
The growing demand for higher performance in the storage and access of data in various consumer electronic and computing devices has driven the development of nonvolatile memory (NVM) technologies. The promising candidates for future NVM such as FeRAM and PCM have demonstrated shorter access time, faster programming and wide read/write bandwidth in the chip and the memory macro. Resistive memory (ReRAM)...
Record 9nm half-pitch functional Transition-Metal-Oxide based Resistive Random Access Memory (TMORRAM) cell and the lowest reported 1μA programming current (Iprog, both Set and Reset) have been achieved with thermally oxidized sub-stoichiometric WOx and Nano Injection Lithography (NIL) technique. The unexpectedly low programming current at 9nm diameter has been examined in-depth, it offers potential...
Vertical double gate floating body (FB) Z-RAM memory cell technology fabricated on a recess gate DRAM technology is presented. Cell operating voltage of 0.5V with comparable static retention and > 1000× improvement in dynamic retention is reported. The reported vertical double gate FB cell is the cell with the lowest operation voltage reported to date.
A zero-cost embedded high density MTP NVM with extensive statistical verification is presented. The family of compact single Poly modules ranging from 64 bit to 64 kbit is based on the Y-Flash concept, employing original array architectures and implemented in standard and power management (PM) 0.18 μm CMOS process flows. No special HV devices or additional masks are employed. Excellent reliability...
A 64Mb NAND-compatible non-volatile memory testchip based on a conductive metal-oxide technology is developed in 0.13μm technology. The memory cell, which does not require a selection device, occupies 0.17μm2 and is built at the intersection of two metal lines above the CMOS circuitry. The chip uses 4 layers of cross-point arrays. Decoding and sensing techniques are also described.
A 3.4 Mb SRAM macro is developed with a built-in stability sensor for adaptive wordline under-drive (AWLUD) in 32 nm HK-MG CMOS technology. By tracking temperature, voltage and process variation of each die, the AWLUD is shown to lower VCCmin by 130 mV, increase yield by 9% at a target frequency, and is projected to reduce test time up to 40% by eliminating die-by-die WLUD programming.
Floating gate cell array reliability associated with high-bit-count per cell (multi-level cell with >=3 bit/cell) is investigated. A high operating voltage during P/E operation can cause excessive charge injection into the inter-poly-dielectrics layers (IPD), and subsequent charge displacement will cause data retention or read-disturb problems. The Vt shift due to this charge displacement is related...
The reliability of advanced embedded non-volatile memories has been discussed using the 2T-FNFN devices example. The write/erase endurance and the data retention are the most important reliability parameters. The intrinsic reliability mechanisms can be addressed through single cell evaluation, while the cell-to-cell variation determines the product level reliability. The cell-to-cell variation can...
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