The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Metal as floating gate (FG) in combination with high-k interpoly dielectrics (IPD) is seen as a possible solution to continue the scaling of NAND Flash technology node beyond 25nm. We have investigated the thermal stability of TaN metal as FG in combination with Hf based high-k IPD stacks. IPD leakage is found to worsen with high temperature anneal and causing degraded memory behavior. Comparative...
CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of key devices for high performance and low power advanced LSIs in the future. In addition, the heterogeneous integration of these materials with Si can provide a variety of More-than-Moore and Beyond CMOS applications, where various III-V/Ge functional devices can be co-integrated. In this presentation, we review...
We present the first demonstration of a III-V MOSFET heterointegrated on a large diameter Si substrate and fabricated with a VLSI compatible process flow using a high-k/metal gate, self-aligned implants and refractory Au free ohmic metal. Additionally, TXRF data shows that with the correct protocols III-V and Si devices can be processed side by side in the same Si fabrication line The Lg = 500 nm...
We investigated structural and electrical properties of Ge and Si metal oxide semiconductor (MOS) devices with Pt/HfO2 gate stacks. Post-metallization annealing in O2 ambient reduced the accumulation capacitance more significantly in Si devices than in Ge devices due to the increase in the thickness of a low-k interfacial layer in-between the HfO2 film and Si substrate. Ge devices exhibited lower...
Impact of area scaling (especially narrow channel) on Vt lowering by La incorporation in high-k gate NMOSFETs is reported for the first time. It is clarified that Vt becomes higher in narrower channel for La-containing high-k gate. Efforts are made to ascribe the strong dependence of Vt on gate width to less effectiveness of La compared to wider channel. Influence of channel orientation at STI edge...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
The HfO2/Hf stacked film has been applied as the gate dielectric in MOS devices. The HfO2 thin film was deposited on p-type (100) silicon wafers by atomic layer deposition (ALD) using TEMAH and O3 as precursors, Prior to the deposition of HfO2 film, a thin Hf metal layer was deposited as an intermediate layer. The deposition temperature of HfO2 thin film was 350degC and its resulted thickness was...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.