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In this letter, we report the heterogeneous integration of vertically aligned silicon (Si) microprobe arrays/(111) with MOSFET circuits/(100) by IC processes and subsequent selective vapor-liquid-solid (VLS) growth of Si. A hybrid Si-on-insulator (SOI) substrate with different species of Si layers, e.g., a (100)-top-Si/buried oxide/(111)-handle-Si system, was utilized for the heterogeneous integration...
Si recess structure formed by plasma-induced physical damage and its effects on the device performance were studied. The depth of Si recess region (dR) was determined from the experiments by using an inductively coupled plasma reactor with simple Ar gas mixtures. Threshold voltage shift (DeltaVth) of n-ch MOSFETs with the recess structure was modeled by using device simulation for various dR. The...
Impact of area scaling (especially narrow channel) on Vt lowering by La incorporation in high-k gate NMOSFETs is reported for the first time. It is clarified that Vt becomes higher in narrower channel for La-containing high-k gate. Efforts are made to ascribe the strong dependence of Vt on gate width to less effectiveness of La compared to wider channel. Influence of channel orientation at STI edge...
To enable medical implants such as artificial retina, smart stent microsensors and other implantable wireless sensors, we developed a biocompatible and flexible RF CMOS technology based on a 0.18 mum CMOS process on 8-inch SOI (silicon on insulator) wafers. The silicon substrate for MOS transistors is 1 mum thick and sandwiched between two parylene layers. Since the potential implantable microsystems...
Drain-induced barrier lowering in substrate-induced strained-Si n-MOSFETs has been investigated. The variation of subthreshold swing as a function of both the gate length and gate to source voltage has also been examined.
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
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