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The Adder is the important part in any processor/controller design. Till date there are a plenty of 1-bit full-adder circuits which have been proposed and designed. In this paper we have a analytic and comparative description of various full adder circuits, considering various constraints like power consumption, speed of operation and area. The circuits are designed in the virtuoso platform, using...
Cache memory plays an important role in high speed electronic devices. SRAM is the key element of cache memory. Cache memory is used for their high speed and SRAM is the element which provides speed to the cache. So this work is mainly concentrated on the simulation and analysis of 8T SRAM cells and their comparative analysis of different parameters such as width to length ratio, capacitance and power...
Domino logic circuits are most often used in high performance designs such as microprocessors because of high speed and less area over the static logic. But these domino logics suffer from high power dissipation and low noise tolerance. In this paper the earlier proposed techniques to reduce power consumption of Domino logic such as Dual Threshold Voltage (DTV), Dual Threshold Voltage-Voltage Scaling...
With the advent of portable and high density microelectronic devices, the minimization of power consumption in CMOS VLSI circuits is becoming a critical concern. An embedded system is a combination of electronic hardware and software and sometimes additional parts designed to perform a dedicated function. In many cases system (microprocessor) must monitor the amount of power it uses and take appropriate...
Dynamic logic style is mainly used for high fan in and high performance circuits because of its smaller area and fast superior speed. This style comes with a problem of low noise margin which makes it more susceptible to noise than static CMOS circuits. It also faces some charge sharing and leakage problems. A small amount of noise at the input can cause an undesirable change at the output. Domino...
CMOS logic is extensively used in VLSI circuits but due to scaling of technology, the threshold voltage of the transistors used in CMOS circuits decrease which cause an increase in leakage power. Dynamic power consumption, which is proportional to square of supply voltage VDD further adds to the overall power dissipation. This results in low battery life of mobile devices. In this brief, a novel method...
Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert...
Multiple Dynamic Supply Voltage (MDSV) is an attractive way to reduce dynamic power in Integrated Circuits. This technique introduces Level Shifter (LS) in order to commute from one voltage domain to another. Nevertheless, some LS inserted during the physical synthesis can degrade performance and power consumption, especially in specific power modes. In this work, we present a novel approach to dynamically...
A three stage single-ended LNA using transformer (TF) matching and gain-boosting by capacitive feedback for wideband operation in the 57–66GHz band is presented. The LNA, fabricated in a 65nm standard CMOS process, achieves a 23dB-gain 4dB NF at 6mA and 1.25V supply, with 2dBm Psat and 0.05mm2 in size, demonstrating best reported noise figure, gain, power consumption and chip area compared to published...
Thermal issues is an important challenge in NanoCMOS chips. High temperatures can reduce the reliability, so it is important to reduce power consumption to improve reliability. It is necessary a change in physical design paradigms to reduce the needed amount of transistors to perform one task. This work shows a new approach to reduce the amount of transistors by using complex gates and a new set of...
This paper presents an ultra low power merged LNA and Mixer design for MICS (Medical Implant Communication Services) applications. A capacitor cross-coupled common gate LNA is implemented for an easy input matching and reasonable noise performance. The mixer operates in weak inversion, which significantly reduces power consumption and relaxes the voltage headroom without sacrificing the LNA performance...
A 0.39 mA 92 dB dynamic range switch-capacitor (SC) third-order ΣΔ modulator for a digital RF hearing aid in 0.35 μm CMOS is presented here. A modified-feedback topology is used here that effectively achieves a high dynamic range and the low power consumption. In the implementation, the bootstrapping-switch and the low-voltage wide-swing OTA are essentially designed for 1.2 V supply voltage with the...
A System-on-Chip (SoC) offers an optimal implementation of electronics for portable medical systems and in particular for Body Area Network (BAN) applications. It integrates as much functionality as possible into a single chip thereby allowing miniaturization of the system, while optimizing performance and power consumption. Using today's mature and cost effective semiconductor process CMOS technology...
A fully differential feedback third-order continuous-time sigma-delta modulator suitable for Mega Hertz wireless communication is presented. Some design optimizations mainly regarding power consumption are demonstrated. The proposed single-bit modulator clocked at 128 MHz achieves 2 MHz signal bandwidth, 11 bits of resolution, 68 dB signal-to-noise ratio and 66 dB dynamic range. Designed in 0.18 μm...
A novel low-power successive approximation register is proposed. The new register is based on gating the clock when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 14 bits has been designed up to the layout level with 1V power supply in 90nm CMOS technology and...
Recently, a wearable body-sensor network realized continuous sleep monitoring by ExG (EEG, EMG, EOG, and ECG) extraction from a sleeper's face. At least 14 sensors were placed on the face, and were managed by a network controller for sleep monitoring. However, the system was too bulky and heavy (127x63.5χ28mnf, 210g) to wear during sleep, and consumed high power (>;100mW). Another system used a...
For WPAN (Wireless Personal Area Network) applications, a low-power low-noise IF (Intermediate-Frequency) circuit is proposed for GFSK (Gauss Frequency Shift Keying) low-IF receivers. The proposed IF system is realized by an all-analog architecture, which is composed of a couple of LAs (Limiting Amplifiers) and RSSIs (Received Signal Strength Indicators), a couple of BPFs (Band-Pass Filters), a FD...
In this paper, we report a low-power voltage-controlled oscillator optimized for an operation around 100 GHz. The ultimate targets of this design are to maximize the oscillation frequency and minimize the power consumption of the oscillator. At the same time, the oscillator must provide a reasonable tuning range and an acceptable phase noise performance. To achieve these stringent requirements, the...
In this paper, we proposed a low noise amplifier (LNA) for ultra wideband (UWB) application using TSMC 0.18μm CMOS technology. To satisfy the wide input matching, LC high-pass filter matching network is utilized in the first stage. To obtain the low power characteristic, folded-cascode with current reused technique is utilized in the second stage. The designed UWB LNA has the voltage gain of 17.6...
In this letter, a 2 × 2 thermo-optic waveguide-based switch with ultralow power consumption is demonstrated and fabricated using a standard complementary metal-oxide-semi conductor (CMOS) process. The phase arms are suspended by removing adjacent SiO2 and 120 μm of the underlying Si, while leaving a few SiO2 beams to support the suspended phase arms for the purpose of structural strength. As compared...
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