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We have studied low temperature processes for monolithic 3D integration platform development including hydrogen/helium ion implantation-based wafer cleavage & bonding (< 450°C), low temperature (< 550°C) in-situ doped S/D selective SiGe epi process, low temperature (< 200°C) gate stack on the chemical-mechanical polished (CMP) wafer, and green-lased annealing. These unit technologies...
3D WLCSP using via last TSV (through silicon via) technology is an ideal packaging technology to meet small-form-factor, high I/O density, high-speed and most important, lower cost. For thin 3D WLCSP with TSVs, a number of critical processes need to be developed such as oxide etch, via cleaning and wafer de-bonding. In the present paper, processes for 8 inch, thin WLCSP with TSV diameter of 40µm and...
A new temporary bonding technology has been demonstrated, where both spin-on glass (SOG) and hydrogenated amorphous silicon (a-Si:H) were used as a bonding layer and as a debonding layer, respectively. Square chips were bonded to a glass wafer through the SOG layer and a-Si:H layer. The SOG bonding was capable of withstanding chip thinning and high-temperature chemical vapor deposition (CVD) processes...
The effect of bulk chemistry of deposited oxide materials on the eventual wafer bonding energy was fundamentally studied. Although low-temperature silicon oxide (LTO) and tetraethyl orthosilicate (TEOS) exhibited the same bulk density, and nitrogen plasma generated a higher degree of surface activation for TEOS than LTO, using LTO as the bonding oxide resulted in a much higher bonding energy than...
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