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Hybrid pixel detectors are now widely used in particle physics experiments and at synchrotron light sources. They have also stimulated growing interest in other fields and, in particular, in medical imaging. Through the continuous pursuit of miniaturization in CMOS it has been possible to increase the functionality per pixel while maintaining or even shrinking pixel dimensions. The main constraint...
The paper demonstrates a low-cost flexible wireless microsystem fabrication technology combining the previously developed bumpless RFSOP scheme with a special surface cleaning process to assemble a CMOS chip with an organic substrate (SU-8/PDMS) by Au-Au thermocompressive bonds (<;200°C). About -15dB return loss and -0.8dB insertion loss @ 40GHz interconnecting structure and above 6MPa bonding...
In this paper, an embedded wafer level package with Cu through mold via (TMV) interconnects was developed for package on package (PoP) application. Cu pillar interconnects for different heights were fabricated on daisy chain test chips and sacrificial chips. The daisy chain test chips were then stacked onto the sacrificial chips using die attach film, and the chip stacks were picked and placed onto...
This paper will focus on recent results of Cu-Cu non-thermo compression bonding for wafer-to-wafer 3D stacking. We report on bonding quality, wafer-to-wafer alignment accuracy and electrical connectivity. Specific pre-bonding surface conditioning is necessary to insure high bonding quality of patterned Cu wafers. A particular concern is related to the planarization (e.g. CMP) of Cu-SiO2 hybrid surfaces:...
For the demands of multifunction, high density interconnection, high performance and integration of homogeneous or heterogeneous ICs, three dimensional IC (3DIC) packaging technologies by through silicon via (TSV) and microbump were widely studied recently. Intending to learn the reliability performance of Pb-free microjoints, 4 chips were interconnected with one Si interposer by Sn2.5Ag microbumps,...
Recently the requirement for portable products, such as mobile phones, digital cameras, PDAs and game consoles, has been increasing rapidly and consumers want to easy to carry them and have multi-functions as well as lower price. So it's necessary to develop the semiconductor packages with thin and small size, high performance and low cost. And various types of SiP (system in package) technologies...
Demand for Through Silicon Via (TSV) is being driven by the need for 3D stacking to shorten interconnection length, increase signal speed, reduce power consumption and reduce power dissipation. Increasing demand for new and more advanced electronic products with a smaller form factor, superior functionality and performance with a lower overall cost has driven the semiconductor industry to develop...
An innovative die to wafer stacking is proposed for 3D devices. Known good dices are bonded on a processed wafer thanks to direct bonding. Oxide layers or patterned oxide/copper layers are used as the bonding medium. After a first thinning, a low stress high deposition rate oxide is deposited to embed the dices. A final thinning is then done to recover a flat and smooth surface before the trough silicon...
This paper reports a hermetic MEMS package structure with silicon wafer as bonded cap at wafer-level scale. CMP followed by spraying chemical smoothing process is utilized to thin the N(100) silicon cap wafer to the thickness of 150 mum after wafer-level Cu/Sn isothermal solidification bonding. Method for the thinning process and parameters for Cu/Sn isothermal solidification bonding process are researched...
We have been developing a novel Wafer Level Packaging technology which has a possibility of lowering WLP cost drastically by applying some Jisso techniques to WLP manufacturing processes. In short, our idea is laminating a Cu wafer having Cu bumps to a Si wafer in which LSIs are formed with a nonconductive thermosetting resin. The process flow of the developed WLP technology is as follows; 1. Cu bump...
A 300-mm wafer-level three-dimensional integration (3DI) process using tungsten (W) through-silicon vias (TSVs) and hybrid Cu/adhesive wafer bonding is demonstrated. The W TSVs have fine pitch (5 mum), small critical dimension (1.5 mum), and high aspect ratio (17:1). A hybrid Cu/adhesive bonding approach, also called transfer-join (TJ) method, is used to interconnect the TSVs to a Cu BEOL in a bottom...
An interconnection scheme which has the merits of align-insensitivity and wafer bonding compatibility is suggested for wafer stacked structure with the silicon through-wafer-via. The interconnection structures in the previous works using a prominent copper solder and metal reflow technique have alignment problems when wafers are bonded for stacking. The suggested modified interconnection scheme prevents...
A new ISM (image sensor module) WLP (wafer level package) for reflow process is designed, fabricated and tested. The ISM WLP is composed of polymer bonding layer, glass cap wafer for particle free process and CIS (CMOS Image Sensor) chip wafer which has micro via hole interconnection. During the last decades, WLP is highlighted as the next generation ISM Package method for many advantages like high...
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