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SOI FinFET transistors have emerged as novel devices having superior controls over short channel effects (SCE) than the conventional MOS transistor devices. However despite these advantages, these also exhibit certain other undesirable characteristics such as corner effects, quantum effects, tunneling etc. Usually, the corner effect deteriorates the performance by increasing the leakage current. In...
Stacked multichannel transistor architectures were proposed recently which possess very attractive electrical characteristics on low leakage current and high driving current per layout area. However, due to complex manufacturing process, the process variation effect is inevitable and whose impact is unknown. Therefore, this study investigates the impact of process variation on 15-nm-gate stacked multichannel...
We have developed a full quantum transport simulator for p-type Si nanowire field effect transistors based on the k??p Hamiltonian. The NEGF formalism was employed for transport calculation and the self-consistent calculations were performed. We have constructed the Hamiltonian in the modespace, with its size greatly reduced compared to the full Hamiltonian. A computationally demanding problem of...
After forty years of advances in integrated circuit technology, the scaling of Silicon Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has entered the nanometer dimension with the introduction of 90 nm high volume manufacturing in 2004. Presently at 45 nm going to 32 nm node in 2009, the latest technological advancement has led to low power, high-density and high-speed generation of microprocessors...
The silicon pillar thickness effect on vertical double gate MOSFET (VDGM) fabricated by implementing oblique rotating ion implantation (ORI) method is investigated. For this purpose, several silicon pillar thicknesses tsi were simulated. The source region was found to merge at tsi < 57 nm, forming floating body effect. The electron-hole concentration along the channel and the depletion isolation...
The static and large-signal behaviour of a new model for a submicron partially-depleted (PD) body-tied (BT) silicon-on-insulator (SOI) MOSFET was recently shown to give excellent agreement with measurements. Here, we complete the model validation with a detailed study of its small-signal capabilities up to a frequency of 50 GHz. Additionally, a new direct procedure is described enabling the extraction...
A simple, area and power-loss efficient, portable and robust ESD protection method for DC/DC converters is presented. The method is based on MOS transistors operating in normal mode, replacing the snapback based design methods. Measurement results of a prototype fabricated on silicon showed good agreement with simulation and are reported.
The ESD sensitivity of 65-nm fully depleted SOI MOSFETs (with thin silicon body) used as output buffer devices is studied. A detailed electrical investigation is carried out in order to classify the observed failure modes and mechanisms. We propose a new failure criterion that allows us to univocally identify the device failure. Finally, we analyze the impact of device geometry and strain engineering...
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