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As a basic block of a multi-switching-and-processing system, fast and fair arbiters are critical to the efficiency of multi-core computing units, high-speed crossbar switches and routers, which are the key to the performance of on-chip networking/computing in a SoC and NoC. In this paper, a High-Speed and decentralized round-robin arbiter (HDRA) is presented. Unlike the conventional round-robin arbiters,...
This paper demonstrates how to rapidly build useful, and high performance self-timed or elastic communication networks. The networks are elegantly extensible to include an arbitrary number of Producers and Consumers. Each switch within the network is built from multiple instances of a Latch Control Element (LaCkEy). The Lackey is a general circuit for self-timed data control. It is built once and...
A parametron-like ternary logic element utilizing 3rd subharmonic oscillation and 3-cycle excitation is considered. By representing the oscillation phase as a vector or phasor, the basic logical operation can be described as a majority operation for vector sum of input signals. Contrary to a delay operation of phase pi (NOT operation) in parametron, two delay operations of phase 2pi/3 and 4pi/3 need...
We propose a novel synthesis method of a dual-rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints. The logic is implemented as a minimized AND-OR structure, together with the completion detection logic. We formulated and proved the product term minimization constraint that ensures a correct logic behavior. We processed the...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
Conventional fast switching measurement method for NBTI characterization, which relates linear drain current degradation DeltaId to threshold voltage shift |DeltaVt| based on the first-order expression |DeltaVt| = intpartId/gm, is shown to severely overestimate |DeltaVt|. By taking into account the effect of source/drain series resistance and vertical-field induced mobility reduction, results obtained...
Most network operators have considered reducing Label Switched Routers (LSR) label spaces (i.e. the number of labels that can be used) as a means of simplifying management of underlaying Virtual Private Networks (VPNs) and, hence, reducing operational expenditure (OPEX). This letter discusses the problem of reducing the label spaces in Multiprotocol Label Switched (MPLS) networks using label merging...
It is generally recognized that asynchronous operation of logic networks offers specific advantages over synchronous operation controlled by a central clock when the network is subject to large or widely varying inter-module propagation delays. In this paper we characterize several previously described techniques for achieving asynchronous operation by a single model. Essential to the model is the...
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