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Electronic System Level (ESL) design flow tries to handle the complexity of today's System-on-Chip design and verification. Due to this complexity, design and verification methodologies start from an abstraction level higher than Register Transfer Level (RTL). In ESL, verification becomes a major bottleneck in the design flow, and finding a good verification methodology at this abstraction level is...
Image processing algorithms applied on programmable embedded systems very often do not meet the given constraints in terms of real time capability. Mapping these algorithms to reconfigurable hardware solves this issue, but demands further specific knowledge in hardware development. The design process can be accelerated by code generation through high-level synthesis, which is very flexible. However,...
Flexibility and high efficiency are common design drivers in the embedded systems domain. Coarse-grained reconfigurable coprocessors can tackle these issues, but they suffer of complex design, debugging and applications mapping problems. In this paper, we propose an automated design flow that aids developers in design and managing coarse-grained reconfigurable coprocessors. It provides both the hardware...
Writing test benches is one of the most frequently-performed tasks in the hardware development process. The ability to reuse common test bench features is therefore key to productivity. In this paper, we present a generic test bench, parameterised by a specification of correctness, which can be used to test any design. Our test bench provides several important features, including automatic test-sequence...
Computer architects are increasingly interested in evaluating their ideas at the register-transfer level (RTL) to gain more precise insights on the key characteristics (frequency, area, power) of a micro/architectural design proposal. However, the RTL synthesis process is notoriously tedious, slow, and errorprone and is often outside the area of expertise of a typical computer architect, as it requires...
Extracting information from unstructured text data is a compute-intensive task. The performance of general-purpose processors cannot keep up with the rapid growth of textual data. Therefore we discuss the use of FPGAs to perform large scale text analytics. We present a framework consisting of a compiler and an operator library capable of generating a Verilog processing pipeline from a text analytics...
The recent introduction of advanced hardware architectures such as the Micro Telecommunications Computing Architecture (MTCA) caused a change in the approach to implementation of control schemes in many fields. It required the development to move away from traditional programming languages (C/C++) to hardware description languages (VHDL, Verilog), which are used in FPGA development. With MATLAB/Simulink...
We propose a design approach to integrating correct-by-construction formal modeling with hardware implementations in VHDL. Formal modeling is performed within the Event-B framework that supports the refinement approach, i.e., stepwise unfolding of system properties in a correct-by-construction manner. After an implement able model of a hardware system is derived, we apply an additional refinement...
In this paper, we propose ArchHDL as a new language for hardware RTL modeling and high-speed architectural evaluations. ArchHDL enables an RTL modeling based on C++ and is unique because it treats registers as variables and wires as functions using the lambda expression which newly defined in the C++11. The simulation speed with ArchHDL compiled by GCC is faster than the speed with Verilog HDL compiled...
In recent years, automatic software verification has emerged as a complementary approach to program testing for enhancing software quality. Finding bugs is the ultimate aim of software verification tools. How do we best support the programmer who has to diagnose and understand those bugs? Unfortunately, most of the existing tools do not offer enough support for error diagnosis. We have developed a...
Dynamic Partial Reconfiguration (DPR) enables software-like flexibility in hardware designs by allowing some of the logic on a Field Programmable Gate Array (FPGA) to be reconfigured while the rest continues to operate. However, such flexibility introduces challenges for verifying DPR design functionality because there is no straightforward way to simulate DPR at Register Transfer Level (RTL). This...
Reconfigurable architectures are object of many studies that try to find tools for a more efficient way of programming, and friendly for software engineers. In spite of the recent advances, there are some applications in which the generated circuits are quite far from optimal. In this paper, we describe a resynthesis methodology, which is suitable for usual multimedia applications. This method transforms...
Reconfigurable hardware such as FPGAs are being increasingly employed for application acceleration due to their high degree of parallelism, flexibility and power efficiency — factors which are key in the rapidly evolving field of embedded real-time vision. While recent advances in technology have increased the capacity of FPGAs, lack of standard models for developing custom accelerators creates issues...
Lime is a new Java-compatible and object-oriented language designed to make programming of reconfigurable hardware significantly more accessible to skilled software developers. Lime programs may run either in software (via Java bytecodes) or in hardware (via behavioral and logic synthesis). This paper illustrates the salient synthesis-oriented features of the language using a photomosaic algorithm...
The paper proposes DDPSL (Drag and Drop PSL) a template library and a tool which simplifies the definition of PSL (Property Specification Language) formal properties by exploiting PSL-based templates. DDPSL allows users not expert in formal methods to define PSL properties by dragging and dropping logical and temporal operators, and variables from the design under verification (DUV) into predefined...
Although the performance of traditional PLC technology is adequate for the majority of industrial automation and control tasks, there exist a number of demanding applications, which need more powerful alternatives. One such alternative, which has received considerable research interest in recent years, is the implementation of control algorithms on FPGAs. An inherent difficulty of this approach is...
The inherent parallelism of the logic resources, the flexibility in its configuration and the performance at high processing frequencies makes the field programmable gate array (FPGA) the most suitable device to be used both for real time algorithm processing and data transfer in instrumentation modules. Moreover, the reconfigurability of these FPGA based modules enables exploiting different applications...
The article introduces the Multiplatform Library Configuration and Tuning Tool (MLCTT) system idea. Today there are many complex projects with digital hardware, where fast speed, low development cost and low power consumption are required. We hope that presented idea can be a good solution for this problem. The introduced MLCTT system is combination of Multiprocessor System on Chip and Multi Core...
Reconfigurable network hardware makes it easier to experiment with and prototype high-speed networking systems. However, these devices are still relatively hard to program; for example, requiring users to develop in Verilog or VHDL. Further, these devices are commonly designed to work with software on a host computer, requiring the co-development of these hardware and software components. We address...
A verification environment which is based on a constrained random layered test bench using SystemVerilog OOP is implemented in this paper to verify the functionality of DUT designed with synthesizable constructors of SystemVerilog. Although the uses of multiple inheritance in OOP appear to be less common than those of single inheritance, multiple inheritance is useful for creating class types that...
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