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One trend for signal processing hardware is the increasing integration of different functionalities in one mixed-signal chip. But the additional integration of analog components on one chip with digital components and a micro-processor like in the Programmable System on Chip (PSoC) from Cypress is accompanied with the extension of the design space and the need to explore it by evaluating different...
H.265 (HEVC) is the latest joint video coding standard with ITU-T SG16 WP and ISO/IEC JTC1/SC29/WG11. Its coding efficiency is about two times compared to H.264. However the burden of coding unit (CU) mode decision with rate distortion optimization (RDO) is too costly to implement it with hardware. The key idea of this paper is a novel mode decision architecture to reduce the HW complexity of RDO...
The appearance of the new MPEG-4 standard offers opportunities for real-time implementations of MPEG-4 encoders suitable for a wide range of applications, including video conferencing, digital storage media, television broadcasting, Internet streaming, and communication. With the rapid development of FPGA, SOPC has been paid great attentions in the area of image and video processing in recent years...
The new generation of field programmable gate array (FPGA) technologies enables an embedded processor intellectual property (IP) and an application IP to be integrated into a system-on-a-programmable-chip (SOPC) developing environment. Therefore, in this paper, we present an efficient HW/SW codesign architecture for JPEG encoder and its FPGA implementation. It consists of a NIOS II processor that...
Mobile video processing as defined in standards like MPEG-4 and H.263 contains a number of timeconsuming computations that cannot be efficiently executed on current hardware architectures. The authors recently introduced a reconfigurable SoC platform that permits a low-power, high-throughput and flexible implementation of the motion estimation and DCT algorithms. The computations are done using domainspecific...
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