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This work studies implementations of the Perception [1] and TAGE [2] branch predictors for general purpose, in-order pipelined single core soft processors. It proposes FPGA-friendly optimizations whose goal is to achieve high operating frequency. This work discusses the design tradeoffs and proposes a highly accurate and fast branch predictor variant based on TAGE, O-TAGE-SC. It operates at 270MHz,...
Productivity for digital circuit design is being outpaced by the rate at which silicon is growing. Complex designs take a significant amount of engineering hours to complete in both ASICs and FPGAs. Design reuse can potentially decrease cost and increase design productivity. The central thesis of this paper is that design productivity could be enhanced by assisting the designer in discovering archived...
Although redundant addition is widely used to design parallel multioperand adders for ASIC implementations, the use of redundant adders on Field Programmable Gate Arrays (FPGAs) has generally been avoided. The main reasons are the efficient implementation of carry propagate adders (CPAs) on these devices (due to their specialized carry-chain resources) as well as the area overhead of the redundant...
Most field programmable gate array (FPGA) devices have a special fast carry propagation logic intended to optimize addition operations. The redundant adders do not easily fit into this specialized carry-logic and, consequently, they require double hardware resources than carry propagate adders, while showing a similar delay for small size operands. Therefore, carry-save adders are not usually implemented...
This paper reports the design of two courses, "embedded hardware'' and "embedded software" offered in 2008 spring semester at Hiroshima University. These courses use 16-bit processor TINYCPU, cross assembler TINYASM, and cross compiler TINYC. They are designed very simple and compact: The total number of lines of the source code is only 427. Thus, students can understandthe entire design...
Decimal arithmetic is important in several commercial applications including financial analysis, banking, tax calculation, currency conversion, insurance, and accounting. This paper presents a fully parallel Decimal64 floating point (FP) multiplier compliant to IEEE Std 754-2008 for floating point arithmetic. The proposed multiplier possesses novel methods to target low latency. The proposed design...
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