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High-speed routers rely on well-designed packet buffers that support multiple queuing, large capacity and short response times. Some researchers suggested a combined SRAM/DRAM hierarchical buffer architecture to meet these challenges. However, both the SRAM and DRAM need to maintain a large number of dynamic queues which is a real challenge in practice and limits the scalability of these approaches...
The inherent support in routers (SNMP counters or NetFlow) is not sufficient to diagnose performance problems in IP networks, especially for flow-specific problems and hence, the aggregate behavior within a router appears normal. To address this problem, in this paper, we propose a Consistent NetFlow (CNF) architecture for measuring per-flow performance measurements within routers. CNF utilizes NetFlow...
Network delay is a major design parameter for Networks-on-Chip (NoC)-based applications. Improving NoC delay could be achieved at different design phases. At the system level, we study in this paper the impact of the network topology on NoC system delay using graph-theoretic concepts. A topology-based model is developed to calculate the average NoC delay, which is caused by links and routers. The...
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