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This paper describes and demonstrates the viciLogic platform as an effective pedagogical solution for online technology enhanced learning, assessment and prototyping of digital logic and computer architecture systems. viciLogic provides an opportunity to improve digital systems education globally and to develop the global digital logic design community, with a positive impact on future digital logic...
Different approaches for implementing a complex multiplier in pipelined FFT are considered and implemented to find an efficient one in this paper. The design is implemented in VHDL and design is synthesized on FPGA to know the performance. The design is implemented with a focus of reducing the resources used. Some approaches resulted in the reduced number of DSP blocks and others resulted in reduced...
The future of hardware development lies in massively parallel hardware architectures as used in embedded as well as high-performance systems, for instance streaming-based, realtime and database applications. Especially field-programmable gate arrays provide a platform for the rapid development of integrated circuits and the accompanied software. For reasons of energy efficiency, it is increasingly...
Placement and routing run-times continue to dominate the automated FPGA design flow. As the size of FPGA architectures continue to grow exponentially, it remains critical to develop parallel tools for FPGA design where the amount of exposed concurrent work scales with the size of the designs to be synthesized. In this paper, we propose a novel algorithm for parallel placement, based on simulated annealing,...
The future of hardware development lies in massively parallel hardware architectures as used in embedded as well as high-performance systems, for instance streaming-based, real-time and database applications. Especially field-programmable gate arrays provide a platform for the rapid development of integrated circuits and the accompanied software. For reasons of energy efficiency, it is increasingly...
This paper presents an efficient design-space exploration method to identify the Pareto solution for the relation between the execution time and the hardware area. Initially, our method takes a particular system mapping that is surely in the Pareto solution, and then repeats the local search and the update of the Pareto solution until the Pareto solution reaches a steady state. Compared to genetic-algorithm-based...
Partial dynamic reconfiguration has become an important feature of FPGA-based systems as the number of applications which use this capability has increased. For systems using multiple partial bitstreams, the complexity of the target reconfigurable region, which often include heterogeneous blocks such as block RAMs and DSP blocks, makes it difficult to generate a unique bitstream which can be loaded...
The time-to-digital converter(TDC) aims to mark an accurate timestamp at the time of input signal comes. The Multi-phase Clock sampling method is an usual way to map the TDC into an FPGA. Traditionally, this method provides a medium accuracy and low resources occupation. In this paper, we present a new architecture of TDC base on the 2-ISERDES in the SelectIO, rather than utilizing the Slice resources...
This paper presents a memory hierarchy with the support of network-on-chip (NoC) for MPSoC systems. The memory hierarchy consists of a shared global memory and private local memories. Each core in the system is equipped with two local memories, one for instructions and one for data. Those local memories are connected through a NoC for efficient data communication. We tested two different settings...
In this poster, we introduce Harmonica, a customizable FPGA-hosted core for massively parallel data intensive applications, designed for use in the proposed Cymric processor-near-memory architecture. We also discuss the deployment of Harmonica in the Cymric prototype, its first use in a full FPGA-based system incorporating a memory hierarchy. Given the nascent state of processor-near-memory (PNM)...
Fault handling is an important metric for many operating environments. The traditional technique for improving reliability of system is by replicating the system component. This paper explains about the Adaptive group testing technique for isolating the faults which is present in the memory of the system. The memory element contains many cell and these cells are grouped into number of blocks. These...
This paper presents direct implementation of parallel Particle Swarm Optimization (PSO) algorithm on Field Programmable Gate Array (FPGA). In the proposed design, the particle unit architecture is independent of fitness unit and hence the particle unit is reusable and flexible for different fitness function. The parallel co-processor implementation of each particle accelerates the execution speed...
Floating point addition is a frequently used operation in real time applications and image processing. Its structure is complex due to multiple shifts, addition and normalization units which increase the latency of operation. In order to have the high performance low latency is desired along with higher throughput. In this paper we have used non-linear pipelining concept to divide the adder operation...
Most network services are provided by middle boxes at present. However middle boxes would cause many issues such as robustness, security and so on. The latest studies put forward the outsourcing mechanism to solve these problems. Given the benefits of FPGA (Field Programmable Gate Array) in reconfiguration and packet processing, we propose Search, an architecture that enables FPGA-based platforms...
This paper focused on the design of 32 bit IEEE 754 single precision floating point architecture for 8 point FFT. The total design is in combinational form. The FFT design is simulated in Active HDL. Results are verified with MATLAB simulation. Correctness is obtained up to twenty two bit. The design is tested for complex input data (separately for real and imaginary data). For low power design pipelining...
This proceeding is compiled from our previous works, where architecture of the Second-Generation Real-Time Cellular Neural Network (CNN) Processor (RTCNNP-v2) was proposed. The system is designed for applications where highresolution and high-speed is desired. The structure is fully-pipelined and the processing is real-time. Proposed structure is coded in VHDL and realized on two FPGA devices: one...
In this paper, a new hardware implementation of the Border-Preserving Interpolator is presented. The object of this proposed work is to achieve significant run time performance using a hardware development board. It also demonstrates consistent image quality performance among a variety of images. This validation show that our implementation based on HW/SW design speeds up the interpolation process...
Artificial bee colony (ABC) is an optimization algorithm inspired on the intelligent behavior of honey bee swarms. It is suitable to be applied when mathematical techniques are impractical or provide suboptimal solutions. As a population-based algorithm, the ABC suffers on large execution times specifically for embedded optimization problems with computational limitations. For that we propose a hardware...
Due to significant technological advances and industry requirements, many universities have introduced programmable logic and hardware description languages into undergraduate engineering curricula. This has led to a number of logistical and didactical challenges, in particular for computer science students. In this paper, the integration of some programmable logic concepts into an introductory digital...
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