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This paper describes the architecture of a flexible and reconfigurable processor for the computation of the state-metric recursion in a multi-standard BCJR decoder. The unit can serve binary as well as duo-binary codes with any number of states. The architecture is arranged into a cluster of state-metric processors plus two multiplexing networks for feedback and normalization, configured on-the-fly...
Over the last years LDPC codes became more and more popular because of their near Shannon limit error correcting performance. Structured code classes which ease decoder design have already been standardized for DVB-S2, IEEE WiMax 802.16e or WiFi. In this paper we introduce a flexible decoder architecture which can decode any structured or unstructured LDPC code using the identical hardware. Furthermore...
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