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In this paper a 0.5 μm NMOS device is used as a High Pressure Sensor by incorporating a Tungsten metal gate (which acts as a Pressure sensing Diaphragm as well) and 1-Mender based serpentine spring at four corner, in a conventional NMOS device. The device is capable of measuring pressures in the range of 10–205 MPa. The sensor, also being a FET device, was also investigated for its AC domain Characteristics...
Accurate estimation of delays in Static Timing Analysis (STA) using Non Linear Delay Model (NLDM) based Look Up Table (LUT) is a major challenge in nanometer range VLSI circuits. Issues with NLDM based LUT are mostly due to the arbitrary choice of input signal transition time trin and load capacitance (Cl) and the large number of simulations to be performed for characterizing an entire standard cell...
The accurate modeling of the MOSFET channel capacitance has evolved from Meyer's reciprocal gate capacitive models to Ward's charge-based, channel partition models. Numerous models have also been proposed to represent trans-capacitive and charging current components. Recently, a solution to separate the transport and charging current components for SOI MOSFET's was proposed. The model also verified...
A design-oriented mathematical model for integrated DC/DC buck converters is presented in this paper. The analysis takes into account the main conduction power loss due to the switches channel resistance in on-state and, starting from the efficiency specification and other constraints, sets the guidelines for the sizing of the output power stage of the DC/DC converter. The model also considers the...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
This paper presents an analytical modeling of ballistic and quasi-ballistic transport, implemented in Verilog-A environment and used for circuit simulation. Our model is based on the Lundstrompsilas approach and uses an expression of the backscattering coefficient given by the flux method. The model takes also into account short channel effects and tales into account the effects of different scattering...
This paper deals with the implementation of a CMOS analog neural network (NN) that has to be integrated in a new kind of optoelectronic measurement system. The aim is to achieve real-time surface recognition using a phase-shift rangefinder and a neural network. NN architecture is a multilayer perceptron (MLP) with two analog input signals provided by the rangefinder, three processing neurons in the...
The inter-electrode capacitances and conductances of polysilicon devices are greatly influenced by the presence of the trap states; accurate numerical simulations of TFT devices show that the peaks exhibited by the low-frequency gate-to-source C-V and g-V curves in the subthreshold regime are associated to large fluctuations of the charge at the edge of the channel due to the trapping-detrapping by...
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