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Since the design and realization of a complex system on a chip is error prone, functional verification should have been a main task in today's design flows but is still underestimated. This paper gives an overview of current modeling approaches to handle functional verification of a design on the top level, prior to tape out. The problems that arise from the different approaches such as baseband modeling...
We consider a high performance software/hardware implementation of fault and fault -free simulation methods, and linting-technology for early design stage verification as well. Application of these technologies allows significant increasing simulation performance in comparison with software tools, and reducing design time of very high scale integrated circuits for 20-30%.
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