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This paper presents a low-power low-IF RF frontend for 2.4GHz wireless sensor networks (WSN) in 0.18μm RF CMOS technology. The RF frontend consists of a variable gain low noise amplifier (VG-LNA), a quadrature passive mixer and a divide-by-two circuit which generates the differential quadrature LO signals for quadrature balanced mixer. The effect of the input parasitic capacitance on the inductively...
This paper presents the design, optimization and methods for test a high frequency high gain low-noise amplifier (LNA), using a UMC RF 0.18 mum CMOS process. The LNA was designed to be part of a low-power/low-voltage RF CMOS transceiver, for operation in the 2.4 GHz ISM band. The LNA has a power consumption of 3.6 mW, for a power supply of only 1.8 V. The LNA has a control signal that makes it to...
Efficiency enhancement techniques in switched Class E power amplifier is usually obtained at the expense of the supply voltage. In cascode topology the supply voltage is limited by the breakdown voltage of the common-gate transistor. So a self biased technique is used at the common-gate to allow RF swing at the gate to boost the biasing voltage above VDD. This enables us to design the PA such that...
An ultra-low power (ULP) SoC including an IEEE802.15.4 2.4 GHz transceiver designed in 130 nm CMOS technology is presented. Power consumption was minimized by using a concurrent system and design optimization to avoid the over-specification of blocks. A novel minimum complexity partial correlation algorithm is used in the digital baseband receiver and drains an average of 4802 A (packet PSDU=20 bytes)...
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