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Conventional design methodologies for EPC RFID tags focused on minimizing the power consumption of each building block to obtain the maximum achievable communication distance. In this work, we analyze different operation states of the RFID tag and their corresponding power consumption characteristics to identify the limiting factor that dictates the communication distance. Based on the analysis, we...
According to meet the requirement of the low power consumption in the handheld RFID reader, it is introduced that a design strategy of power consumption and a scheme of component selection in the design of an handheld RFID reader based on the MSP430F149 MCU, and a method, when combined with the working status of the RFID reader, is proposed to reduce the power consumption through adjusting the clock...
In this paper, an ultra-low-power baseband processor for a UHF Passive RFID Tag is presented. It proposes a prominent RFID tag baseband architecture which is compliant with the ISO18000-6B UHF RFID protocol. Several low-power design approaches are employed to reduce the power consumption, including low voltage low operation frequency approach, clock gating technique, clock strobe design, asynchronous...
An ultra-low power (ULP) SoC including an IEEE802.15.4 2.4 GHz transceiver designed in 130 nm CMOS technology is presented. Power consumption was minimized by using a concurrent system and design optimization to avoid the over-specification of blocks. A novel minimum complexity partial correlation algorithm is used in the digital baseband receiver and drains an average of 4802 A (packet PSDU=20 bytes)...
A dual mode UHF RFID transponder in 0.18 mum CMOS conforming to the EPC Gen 2 standard is presented. Low voltage design of the analog blocks enables the chip to operate with a 1 V regulated voltage thus to reduce the power consumption. The chip operates with -11 dBm and -20 dBm RF signal in passive and battery-assisted modes, respectively. A specific Gen 2 command switches the operation mode of the...
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