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This paper presents a CMOS RF receiver front-end suitable for ultra-low-power operation. In order to achieve desired gain and linearity of receiver front-end at a 1V supply voltage, current reuse and optimum gate biasing techniques are employed. The proposed architecture includes merged LNA and mixer, operating in the sub-threshold region, and designed for the 902–928MHz ISM band. The proposed circuit...
Two 23 GHz low-noise amplifier (LNA) have been designed and implemented by 45 nm planar bulk-CMOS technology with high-Q above-IC inductors. In the designed LNAs, the structure of cascode amplifier with source inductive degeneration is used. All high-Q above-IC inductors have been implemented by thin-film wafer-level packaging (WLP) technology. The fabricated one-stage LNA has a good linearity where...
A two-stage, variable-gain low-noise amplifier (LNA) which offers good matching and good noise performance is demonstrated. A prototype 2.5 GHz LNA is designed and simulated using 0.13 um RF CMOS process technology. The simulated LNA has a maximum gain of 32.6 dB, input return loss of -44.9 dB, and output return loss of -5 dB. It has a noise figure of 1 dB and input P1dB of -33.9 dBm in high-gain...
This paper presents a 24-GHz single-in differential-out (SIDO) CMOS low-noise amplifier (LNA) for wireless communication applications. The SIDO LNA utilizes a trifilar transformer inserted between the first and the second stages for the single-to-differential signal conversion. The LNA, fabricated in a 0.13 mum RF CMOS technology, exhibits a differential gain of 14.7 dB, a 3-dB bandwidth of 3.5 GHz...
A wide band 5.8-10.6 GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. This LNA is used to work for the upper band of ultra wide band (UWB) wireless receivers according to the DS-CDMA proposal. The feedback technique is used to achieve a large bandwidth around 4 GHz. Moreover, this topology helps to cancel the noise of the input matching...
The increasing mask costs of modern scaled CMOS makes silicon area precious. Meanwhile, the lowering oxide thickness seriously toughens ESD protection of RF circuits, pushing towards area-demanding inductor-based ESD protection techniques. This paper presents a transformer-based ESD protection technique for inductor-based LNAs. With no area penalty, an ESD protection level of 4.5 kV HBM is achieved...
In this paper, the aim of this work is to design a V-band low-noise amplifier that is suitable for SoC and wireless communication systems. It achieves a peak gain of 11.7 dB while consuming 21.6 mW.
This paper describes a low-voltage, low-power CMOS RF front-end for wireless sensor networks (WSNs) implementation in the 2.45-GHz band based on IEEE 802.15.4 standard. The design targets a low-IF receiver architecture and consists of a low-noise amplifier and a quadrature mixer that downconverts an RF input at the 2.45-GHz band to an IF at 2 MHz. To promote low cost and low-voltage operation, all...
Scaling of CMOS transistors beyond 45 nm requires architectural redesign of the devices. FinFETs are proposed to recover the reduced channel control. This work evaluates the perspective of RF design in planar bulk vs. FinFET SOI for (sub-)45 nm CMOS on a key RF circuit: a low-noise amplifier (LNA). The planar and FinFET devices with channel lengths down to 40 nm are compared in both wideband and narrowband...
A 0.18-mum CMOS tri-band MIMO transceiver for fixed and mobile WiMAX applications is presented. The transceiver supports operation in the 2.3-2.7 GHz, 3.3-3.8 GHz, or 4.9-5.95 GHz bands. A novel DC-offset removal scheme is used to enable a low-cost direct-conversion architecture. The transmitter exhibits an EVM of -38 dB, -36 dB, and -33 dB @ 0 dBm output power for the 2G, 3G, and 5G bands respectively...
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