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In this paper, a study of the leakage current through strained p+ n Si1-xGex/Si hetero-junctions is presented. The reduction in the band gap, induced by stress forces, and the doping level at the hetero-interface, due to the use of halo implantations, are varied by changing the Ge content and the recess depth. A comparison between simulation results and experimental data is presented to analyze the...
A dual-k spacer concept is proposed and evaluated in underlap and nonunderlap n-channel silicon tunnel field-effect transistors (FETs) for the first time using extensive device simulations. The dual-k spacer consists of an inner layer made of a high-k material and an outer layer made of a low-k material. It is shown that the dual-k spacer improves the performance of n-channel tunneling FETs and more...
By incorporating the realistic junction parameters, we have obtained new insights on practical TFET operation. Interestingly, we have found that a non-abrupt junction does not necessarily degrade the TFET performance if the geometry can be appropriately optimized. We have also studied the tradeoffs in using a Si-Ge-Si channel.
We report for the first time experimental investigations on SOI, Si1-xGexOI & GeOI Tunnel FET (TFET). These devices were fabricated using a Fully Depleted SOI CMOS process flow with high k-metal gate stack, enabling 2 decades lower IOFF (~30fA/mum) compared to co-processed CMOS. We successfully solve the TFET bipolar parasitic conduction by a novel TFET architecture, the Drift Tunnel FET (DTFET),...
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