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We report a novel device which exploits the internally combined quantum mechanical Band-To-Band and Barrier Tunneling mechanisms to achieve improved performances and overcome the intrinsic low current drive limitations of conventional Tunnel FETs and the 60 mV/decade limitation of MOSFETs at room temperature. The new structure, including an ultra-thin dielectric between metal source and silicon channel,...
A direct high-k/Si gate stack has been proposed for gate oxide scaling. With LaCe-silicate, an EOT of 0.64 nm with an average dielectric constant (kav) of 17.4 has been obtained and an extremely low gate leakage current (Jg) of 0.65 A/cm2. The flatband voltage (Vfb) can be controlled by the compositional ratio of La in the LaCe-silicate layer. Furthermore, incorporation of Ge atom into the silicate...
The continuous and systematic increase in transistor density and performance, as described in ldquoMoore's Lawrdquo and guided by CMOS scaling theory, has been remarkably successful for the development of silicon technology for the past 40 years. As the silicon industry moves into sub-ten nanometer dimensions, significant technology challenges in device performance, power dissipation, and variability...
The continuous and systematic increase in transistor density and performance, as described in ldquoMoore's Lawrdquo and guided by CMOS scaling theory, has been remarkably successful for the development of silicon technology for the past 40 years. As the silicon industry moves into sub-ten nanometer dimensions, significant technology challenges in device performance, power dissipation, and variability...
It is well known that the Taiwan Semiconductor industries play the very key roles for the worldwide IC foundry, and the advanced research of nanoelectronics is the lifeline for its long term developments. Professor Huey-liang Hwang effectively integrated the most outstanding research team and resource in Taiwan on the National Project on Nanometer CMOS Transistors for the 21 century, which is sponsored...
Impacts of electron trapping/detrapping on the negative bias temperature instability (NBTI) characteristics in silicon nanowire transistors (SNWTs) with metal gates are experimentally studied in this paper. It is demonstrated that large amounts of as-grown defects, including both electron traps and hole traps, are induced by nanowire structure due to multiple surface crystal orientations of the cylinder...
Effect of the flat band voltage reduction (roll-off) in highly scaled high-k/metal gate stacks is discussed. The proposed mechanism explains the roll-off phenomenon as caused by the metal electrode/high-k dielectric-induced generation of positively charged oxygen vacancies in the interfacial SiO2 layer in the high-k dielectric stack. The model is consistent with the observed roll-off dependency on...
We report on p-MOSFETs based on La2O3, Al2O3 and a mixture of both as high-k dielectric deposited by molecular beam epitaxy (MBE). Mobilities of about 140 cm2/Vs were achieved, which are 1.3 to 1.5 times larger than the universal hole mobility of Si/SiO2. This demonstrates the potential advantage of La2O3-based Ge p-MOSFETs over Si devices. The negative threshold voltages VT, which range between -0...
We report on design flows for the fabrication process of n and p type organic transistors onto a single substrate that allows for the integration of integrated circuits. Our fabrication process employs Cytop as the gate dielectric and four different combinations of organic semiconductors. Two p type organic semiconductors were used, Pentacene and alpha-sexithiophene and two n type semiconductors were...
We demonstrate a low loss metal slot waveguide of deep subwavelength confinement (~lambda/10) and efficient coupling with standard silicon wire waveguides for on chip integration.
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