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We propose a scale-out solution for deep packet processing (DPP) appliances, which uses a standard Ethernet switch in combination with a load balancing controller. The majority of the data-plane traffic is distributed via the switch's built-in traffic distribution function and no connection state is kept. If the load balancing controller detects a skew in the load of the DPP appliances, it updates...
The goal is to distribute UTC(CH) in a remote location via TCP/IP. The MC (Master Clock) is locked to UTC(CH) via a combination of IRIG-B and 1-PPS signals. The SC (Slave Clock) is controlled by a PI control loop that tracks the MC. The SC-MC clock offset and the transmission delay are estimated simultaneously by means of a TW (Two-Way) comparison process similar to NTP but based on TCP/IP.
Targeting the distribution of accurate frequency and time references across Packet Switched Networks (PSNs), the IEEE Std 1588™-2008 (a.k.a. 1588V2 or PTPV2) standard specifies network infrastructure components intended to reduce the impact of network elements located between the Grandmaster clock and Slave clocks. Also referred to as On-Path Supports (OPS), these PTPV2 build-in network components...
Based on the principle of Pipeline ADC, a 10-bit, 50-MS/s pipeline A/D converter is presented in this paper. Combining with bootstrap circuit and bottom-plate sampling technology, a high linearity on-chip sample-and-hold (S/H) is realized. This ADC is optimized for high static and dynamic performance applications in imaging and digital communications. It operates at 1.2 V power supply and achieves...
The substation recording system is independent, the control center can not effectively monitoring on its operational status and cannot achieve more centralized management, cannot immediately find malfunction. So Put forward through the IP networking with straight unicom establish dispatching center of centralized management platform, make recordings in different geographic location of substation scheduling...
This paper presents a Current Mode Logic (CML) transmitter circuit that forms part of a Serializer/ Deserializer IP core used in a high speed I/O links targeted for 10+ Gbps Ethernet applications. The paper discusses the 3 tap FIR filter equalization implemented to minimize the effects of Inter Symbol interference (ISI) and attenuation of high speed signal content in the channel. The paper also discusses...
State of the art VLSI systems are characterised by their small, deca-nano feature size. In order to accommodate the complexity and scalability, a new design paradigm, system on chip (SoC) has been introduced. Performance and power of giga-scale SoC is ever more communication-dominated. However typical SoC communication infrastructure is based in standard buses and protocols which are difficult to...
The paper describes an original design of IEEE1149.1 testing bus controller IP core using reusable technology. We have designed the structure of IP core according to the function of IEEE1149.1 testing bus controller. Every function module of IP core was explained detailedly in this paper, including interface of microprocessor module, command control module, TMS creation module, TCK creation module...
Crossbar switches are fundamental building blocks of digital networks such as the Internet. An input-queued (IQ) crossbar switch includes a set of queues at the input side of the switch, combined with an unbuffered switching matrix with N2 crosspoints. A crosspoint-queued (XQ) crossbar switch contains a FIFO queue at each of the NxN crosspoints of the switching matrix. Switches with combined IQs and...
In this paper, a clustered network on chip (C-NOC) a modified model of Hermes NOC (H-NOC) is introduced. The clustered NOC switch has four local ports. When the packets are switched to local ports, the network traffic load and, consequently, the average delay time of a packet are decreased in group communication. When the distance of nodes in each group are increased in a mesh, the performance of...
A set of SoC low power design methods is presented based system level, IP module level and gate level. These methods were applied to low power design of a SoC. The SoC power simulation results showed that the static and dynamic power of this SoC was quite low. The goals of the low power design methods applied on the design were achieved. The SoC has been implemented in 0.18 ??m COMS process, the area...
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