The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Analog-to-Digital converters plays vital role in medical and signal processing applications. Normally low power ADC's were required for long term and battery operated applications. SAR ADC is best suited for low power, medium resolution and moderate speed applications. This paper presents a 10-bit low power SAR ADC which is simulated in 180nm CMOS technology. Based on literature survey, low power...
The continuous growing demand of portable battery-powered electronics devices hunts for Nano-electronic circuit design for ultra-low power applications by reducing dynamic power, static power and short circuit power. In sequential circuit elements of an IC, a notable amount of power dissipation occurs due to the rapid switching of high frequency clock signals, which do not fetch any data bit or information...
This paper presents a simple circuital technique to design efficient pulse triggered flip-flops. The proposed approach aims at considerably alleviating the detrimental effects of current contention mechanisms, occurring at critical switching nodes during an output switching. In this way, both latency and power consumption are reduced. The proposed approach is assessed by means of simulations in 90-nm...
Dual edge triggering is an effective method for reducing the power consumption in the clock distribution network. This paper compares two existing design of flip-flop CDMFF and CPSFF with the proposed design of the dual edge triggered flip-flop (DE-CPSFF). The design eliminates the redundant transitions of internal nodes when current data is same as the previous one using conditional technique. This...
Saving power consumption is the most important aspect of nanoscale ASIC and system-on-chips (SOCs). At the same time, due to the low supply voltage and reduced node capacitance, nanoscale integrated circuits are highly susceptible to energetic particle-induced transient data upsets (SEUs). In this paper, we propose a high-speed SEU hardened flip-flop. The flip-flop consists of a unique soft error...
A new clock gated flip-flop is presented. The circuit is based on a new clock gating approach to reduce the consumption of clock signal's switching power. It operates with no redundant clock cycles and has reduced number of transistors to minimize the overhead and to make it suitable for data signals with higher switching activity. The proposed flip-flop is used to design 10 bits binary counter and...
A field-programmable device has been developed, specialised for neural signal processing and neural modelling applications. The device combines analogue and digital functions, yet unlike other designs for Field-Programmable Mixed-signal Arrays (FPMA), there is no separation between the analogue and digital domains. To allow analogue values to act directly as inputs to digital blocks, all digital circuitry...
Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper gives a brief overview of low power design principals, then focuses discussion on circuit level methods specifically state-of-the-art low power design techniques of clocking systems. Finally we discuss low power optimization techniques at system and architecture...
In recent years, energy saving techniques have become critical in hardware designs, especially for mobile devices. This paper has reviewed several previous designs of double edge-triggered flip-flops, and has proposed a transmission-gate-based double edge-triggered flip-flop with a clock-gating function. Comparing to the previous work of double edge-triggered flip-flops, the proposed one saved 33...
Power consumption is the bottleneck of system performance and is listed as one of the top three challenges in ITRS 2008. Low power design can be exploited at various levels, e.g., system level, architecture level, circuit level, and device level. This paper first gives a brief overview for low power optimization techniques at system and architecture level, then focus discussion on circuit level methods...
This paper proposes utilisation of polymorphic electronics to design dependable digital circuit controllers. The controller of a general digital circuit is an implementation of a finite state machine. One of most popular implementation is based on a synchronous digital counter. The counter consists of flip-flops and some glue logic. In proposed approach, the glue logic is designed using polymorphic...
The architecture of an asynchronous CMOS Analogue to Digital Converter (ADC) with a binary tree structure exhibiting ultra low die area and power consumption will be presented in this paper. It is based on integer division that is implemented by current mode circuits that operate without a clock signal. Special emphasis is given on the description of the Sample/Hold and Voltage to Current conversion...
This paper demonstrates how to rapidly build useful, and high performance self-timed or elastic communication networks. The networks are elegantly extensible to include an arbitrary number of Producers and Consumers. Each switch within the network is built from multiple instances of a Latch Control Element (LaCkEy). The Lackey is a general circuit for self-timed data control. It is built once and...
A 100 MHz DC-DC switching converter with one-cycle control is proposed for radio frequency power amplifier. All blocks of one-cycle controller are built up on AMI 0.5 mum technology. The power supply has a tracking bandwidth of 5 MHz and an estimated efficiency of 80%. The converter performance is verified by means of simulations.
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random logic is in the order of the number of SRAM cells on chips only a few years ago. Often latches are clock gated and have to retain their states during longer periods. Moreover, miniaturization has led to elevated susceptibility...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
This paper discusses the technology limits placed on the clock switching energy in sequential elements. It proposes a novel pulsed latch that uses a single clocked transistor and consumes close to ten times less clock power than a conventional latch using six clocked transistors. It describes how the new circuit enables additional power savings when virtual grounds, instead of a regular clock, are...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.