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This paper presents a 10-bit 5-5 segmented current- steering digital-to-analog converter implemented in a standard 130-nm CMOS technology. It achieves full-Nyquist performance up to 1 GS/s and maintains 54-dB SFDR over a 550-MHz output bandwidth up to 1.6 GS/s. The power consumption for a near-Nyquist output signal sampled at 1.6 GS/s equals 27 mW. To enable the presented performance a design strategy...
This paper presents a delta-sigma current-steering digital-to-analog converter implemented in a standard 130 nm CMOS technology. The 5-bit core DAC provides 13-bit static linearity without calibration, using only 0:44 mm2. The delta-sigma converter achieves 68 dB SFDR over a 100 MHz signal bandwidth at 1 GHz sampling frequency. A novel very low power thermometer decoder was used, resulting in a power...
A delay-locked loop of multi-band selector with wide-locking range and low power dissipation is presented. The architecture of the proposed delay-locked loop consists of phase frequency detector, charge pump, band selector, multi-control delay line, and start-up circuit. The multi-band selector is used to extend operation frequency of delay-locked loop by switching the multi-control delay line. The...
Regular Current-Steering D/A Converters (CS-DACs) using high-swing cascode current-source structures fail to operate with very-low supply voltages. In this paper, body- driven enhanced-impedance current cells have been employed to satisfy required characteristics of CS-DAC in low headroom voltage. In this technique, a body-driven amplifier increases the output impedance of a cascode current source...
The next generation of wireless communication is a ubiquitous radio system concept, providing wireless access from short-range to wide-area, with one single reconfigurable and adaptive system for all envisaged radio environments. This paper presents the design approach of RCO (reconfigurable concurrent oscillator) that simultaneously generates two or more signals of different frequencies that eliminate...
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