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In this paper, a sample/hold circuit for switched capacitor structure in 0.35 ??m CMOS process technology is described. The sample/hold circuit is used for 14-bit pipelined A/D converter with a conversion rate up to 80 MSPS. In the circuit, the differential unity gain structure is employed. The impact of channel injected charges is reduced through sequential control. The amplifier with a folded cascode...
In this work, the design of a Time-to-Digital Converter (TDC) for measuring the time-of-flight (ToF) of a radio pulse is described. It consists on two blocks: a time-to-voltage transducer, whose scheme is that of a charge pump, designed using a 0.25 mum CMOS process, and an incremental first order sigma-delta (SigmaDelta) converter. The two blocks are connected together by means of a sample and hold...
This paper presents a new scheme of designing a 16-bit Digital to Analog Converter with a Supply voltage of 1.2 Volts. The proposed design combines three different architectures in a novel way so as to achieve low power and low area requirements of the present day technology. The design is targeted to cater the needs of Digital Audio applications. Simulations are done in CADENCE Virtuoso Front to...
This paper proposes the complete electrical design of a new multiply-by-two amplifier to be readily used in high-speed medium/low resolution pipeline ADC stages. It is based in a switched-capacitor open-loop structure but with the novelty of having the gain accuracy improved by using an active amplifier with local feedback. Simulation results demonstrate that, with a very low-power dissipation and...
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