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This paper describes the design and implementation of a reconfigurable low power 180-nm CMOS cascade Σ-Δ modulator for multi-standard wireless communication. Both architectural and circuital reconfiguration is used to adapt its performance to multi-standard applications. Post layout simulation reveals that the prototype achieves 86.82/54.88/66.51d B peak signal-to-(noise+distortion) ratio within bandwidth...
This work presents a new architecture of spread-spectrum clock generator providing 1.5-Gbit/s, 3-Gbit/s and 6-Gibt/s SATA compatible specifications. A two-stage delta-sigma modulator is proposed to simplify the hardware and to overcome the nonlinearity issue of triangular control voltage induced by supply voltage, process and temperature variations. The peak energy of the output clock spectrum is...
This paper proposes a low power dual-mode sigma- delta (SigmaLambda) modulator for GSM and WCDMA receivers. The proposed modulator satisfies both standards by modifying the transfer function without changing sampling frequency or the loop order. The simulation results show 85 dB dynamic range for a GSM mode and 55 dB for a WCDMA mode. The proposed modulator is designed in a 0.35 mum CMOS process and...
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