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A stacked-CMOS SRAM cell with a polysilicon p-channel thin-film transistor (TFT) load that has been attracting much attention as a high-density and low-standby-current SRAM is considered. The authors demonstrate a high-performance stacked-CMOS SRAM cell with remarkably improved polysilicon p-channel TFT load characteristics: a leakage-current of 0.07 pA/μm, and an on/off ratio of 105 at the...
Thin-film transistor (TFT) cell technology has been proposed for high-density SRAM cells. It was demonstrated that when utilizing this technology both low standby current and high cell stability are obtained simultaneously without increasing cell size. TFT characteristics required for 4-Mb SRAMs are discussed, and it is noted that improvements in packing density while maintaining low standby current...
An SRAM cell structure using stacked double-gated, self-aligned polysilicon PMOS thin-film transistors (TFT) is described. This memory cell has been realized in a half-micron, triple-poly, double-metal CMOS process; the cell area is 22.32 μm2, adequate for 4-Mb SRAMs. The main features are: (i) self-aligned structure to precisely define the TFT channel, (ii) TFT drive current enhancement by...
A 25- mu m/sup 2/ poly-Si PMOS load SRAM (static random access memory) cell, called a PPL cell, has been developed. The cell has been excellent retention characteristics, high soft-error immunity, and low standby power. These advantages are achieved using poly-Si PMOS loads and cross-coupled stacked capacitors formed between the NMOS and the stacked poly-Si PMOS. A large poly-Si PMOS ON current lowers...
A novel, simple LOCOS (local oxidation of silicon) technology has been developed for 0.5- mu m MOS devices. Using the technology, channel-stop implantation and deep-channel implantation are performed simultaneously after field oxidation. These self-aligned implantations eliminate the lateral diffusion of the channel stop impurities, thus suppressing narrow-width effects. Moreover, the body effects...
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