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A self-timed SRAM of 18-Kb density has been developed. It has several value-added features for specialty computer CPU applications. This part has an access time of 3.5 ns and a cycle time of less than access. All inputs are registered with respect to the clock positive edge, and read and write operations are internally self-timed. The output latch self-loads internally, thus insuring that data are...
An architecture that improves serial I/O operation speed, reduces layout area, and permits simple control is presented. The architecture features a high-speed, simple configuration, an easy controllable data shifter, and an high-speed redundancy circuit. With this architecture, a 4-Mb field memory with 100-MHz serial access capability has been developed. The process technology used is 1.0 μm...
A single-transistor advanced contactless EEPROM (ACEE) array technology with an 8.6 μm2 cell developed for a single-power-supply 5-V only 4-Mb flash EEPROM is described. This ACEE technology has 0.8 μm minimum lithographic feature sizes and a novel sublithographic remote tunnel diode structure. Low-voltage isolation between bitlines of the same cell has been achieved by diode isolation...
An EPROM cell structure is described that uses folded word lines with double Al layers. Cell characteristics are optimized to obtain high-speed access. The data retention reliability and erasability are studied, focused on a 2Al metallization process. The feasibility of the technology has been confirmed by a 1-Mb CMOS EPROM device which shows 16 ns access time and extremely high data retention reliability...
A full CMOS six-transistor memory cell was fabricated with single-polysilicon, double-metal technology. The channel lengths of n-channel and p-channel transistors are 0.8 μm and 1.2 μm and the cell sizes are 8.5 μm×12.8 μm, respectively. The gate oxide thickness is 200 Å, and the lightly doped drain (LDD) structure is adopted for the n-channel transistor...
An 8-ns serial access time has been realized in a 4-Mb static RAM with newly proposed circuits (hierarchical shift registers and look-ahead circuits) which can access up to 4 Mb. This memory realizes a 125-MHz fast serial READ/WRITE operation suitable for ultra-high-speed memory systems such as image-processing systems, high-speed testing systems, and supercomputers. This function is also beneficial...
A CMOS contactless cell array technology has been developed for a single-power-supply high-density, five-V-only flash memory and for system programmable IC applications. The technology's suitability for VLSI memories has been demonstrated by a 256-kb flash EEPROM (electronically erasable programmable read-only memory) chip. This low-current five-V-only approach has been proved, with cell area and...
A 25- mu m/sup 2/ poly-Si PMOS load SRAM (static random access memory) cell, called a PPL cell, has been developed. The cell has been excellent retention characteristics, high soft-error immunity, and low standby power. These advantages are achieved using poly-Si PMOS loads and cross-coupled stacked capacitors formed between the NMOS and the stacked poly-Si PMOS. A large poly-Si PMOS ON current lowers...
A novel three-dimensional buried trench (BT) memory cell, suitable for DRAM (dynamic random access memories) of 64 Mb or beyond, has been demonstrated. It uses a novel self-aligned-epitaxy-over-trench (SEOT) technology which allows the fabrication of the cell horizontal access transistor in bulk material epitaxially grown over the trench capacitor. The via connection between the access transistor...
SRAM (static random access memory) design and process requirements are used to project technology constraints for the near future. Previous methods for achieving fast SRAMs are reviewed. Trends interfacing the relationship between technology and chip architecture are then examined, including new packaging constraints. The speed limits for SRAMs of increasing density are explored. The increasing importance...
A shallow trench isolation (STI) technology, RIE (reactive ion etching), CVD (chemical vapor deposition) oxide fill, and polarization are used to realize lithography-limited, submicron device and isolation dimensions. A novel boron diffusion technique is used for nMOSFET field doping, so that the parasitic sidewall inversion (leakage) problem is eliminated. It is shown that both the channel width...
The authors describe a single-polysilicon CMOS process that has been optimized for the production of high-speed programmable logic devices (PLDs). The process departs from conventional approaches in two respects: it is a modular addition to a standard CMOS logic process, and it uses a single-polysilicon EPROM cell. The technology has been used to fabricate a 22F10 PLD with an access time of 9.0 ns...
Numerical simulations for the response of inverters to high-energy ion strikes are used to compare the single-event-upset (SEU) hardness of p- versus n-well technologies. A constant-geometry, mirror-image technique is used to generate the technology designs, with the objective of presenting features inherent to the well type. The p-well exhibits better SEU tolerance at low ion energies, but in the...
A contactless cell array technology has been developed for a single-power-supply 5V-only CMOS flash EEPROM (electrically erasable programmable read-only memory). The technology's suitability for VLSI memories has been demonstrated by a 256-kb flash EEPROM test vehicle. This low-current approach has been realized with cell area and cost comparable to those of the recently reported dual-power-supply...
A 5-V-only flash EPROM (erasable programmable read-only memory) cell is described which is programmed by channel-hot-electron injection and erased through a poly-poly oxide. The cell consists of a self-aligned split-gate EPROM and a polysilicon erase line. A charge-pumping technique which takes advantage of very low programming current is used to ensure fast programming at a worst case condition of...
The authors introduce a diagonal active stacked capacitor cell with a highly packed storage node (DASH) for use in a 16-Mb DRAM (dynamic random access memory). This novel cell features a storage capacitor formed above a bit line and the diagonal active area, which provides a large storage capacitance, 35 fF/bit, in a cell size of 3.4 mu m/sup 2/. The average charge retention time measured using an...
A high-performance CMOS technology and cell structure for a megabit EEPROM are described. A novel EEPROM (electrically erasable programmable read-only memory) cell called a stacked floating gate with self-aligned tunnel region (SSTR) cell has been developed. A merged signal transistor structure has been developed to reduce the cell size. A sufficient cell threshold window is obtained in 2 ms at 16...
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