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We present a new class of covert channels which can be created by utilizing common hardware but that cannot be detected by such. Our idea is to abuse anti-EMI features of a processor to create a covert channel on the physical layer. Thus, the sender uses the invariants in how digital signals are encoded over analog channels to covertly transport information. This leaked data is present on the wire...
A virtualized environment (VE) is expected to provide secure logical isolation across the co-located tenants encapsulated in the virtual machines. In particular the VE should prevent covert-channels exploitation stemming from the usage of shared resources. However, as sophisticated covert-and side-channel attacks exist, the logical isolation in a VE is often considered insufficient to raise concerns...
By using covert channels, a malicious entity can hide messages within regular traffic and can thereby circumvent security mechanisms. This same method of obfuscation can be used by legitimate users to transmit messages over hostile networks. A promising area for covert channels is wireless networks employing carrier sense multiple access with collision avoidance (CSMA/CA) (e.g., 802.11 networks)....
We apply and extend the packet detection and frequency synchronization technique by Schmidl and Cox to a multi-antenna receiver for Wireless Access in Vehicular Environments (WAVE) according to IEEE 802.11 p. We investigate the resulting performance enhancements due to the use of multiple antennas from recently carried out real-world experiments in vehicular scenarios. The evaluation shows that the...
In this paper the receiver path of an EPC Class-1 Gen-2 conform RF identification (RFID) Tag Emulator at 868 MHz is presented. The underlying hardware avoids the disadvantages of common tag emulators which emulate the logical behavior only. The implemented EPC Tag Emulator allows the precise emulation of the physical behavior of an UHF RFID tag. Therefore, it can handle worst case test scenarios for...
This paper presents a run-time monitoring framework to detect end-to-end timing constraint violations of event flows in distributed real-time systems. The framework analyzes every event on possible event flow paths and automatically inserts timing fault checks for run-time detection. When the framework detects a timing violation, it provides users with the event flow's run-time path and the time consumption...
An analysis-based framework for the rapid development of a radio receiver for signals with unknown parameters is pro-posed, exploiting the reconfiguration capabilities of FPGAs. The framework guides a non-expert user through the process of signal classification and FPGA-based receiver implementation. System efficiency is traded off with implementation time in order to allow fast radio creation. A...
As deep sub-micron (DSM) technology improves, the need for interfacing modules in multiple clock domains (MCD) is increasing. This work proposes a novel interfacing method for point-to-point communication between modules whose frequencies are rationally related. The introduction of two stages of FIFO-like interfacing registers makes this method skew tolerant. It also allows a slower module to receive...
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