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Secure System is significant part in the data communication. Randomization in the secret keys give raises to the security and complexity of the cryptography algorithms. However, the algorithms are compensating memory spaces and execution time. In Nov 2001 NIST select Advanced Encryption Standards (AES). Field programmable gate arrays (FPGAs), are reconfigurable in nature, low in price and. This paper...
This paper present a novel architecture for image segmentation. The design is based on the fuzzy c-means algorithm based gaussian function in pulse mode for reducing the large storage requirement. The proposed algorithm is tested in mammogram image segmentation approximately with 0.92 of segmentation index. The pulse mode stochastic computing technique is implemented with a simple bloc avoiding the...
In this work, an FFT architecture supporting variable FFT sizes, 128∼2048/1536, is proposed. This implementation is a combination of a 2p point Common Factor FFT and a 3 point DFT. Various FFT output pruning techniques for this architecture are discussed in terms of memory and control logic overhead. It is shown that the used Prime Factor FFT as an FFT in the 1536 point FFT is able to increase throughput...
This paper proposes a novel FPGA implementation of (Vector Directional Distance Rational Hybrid Filter) (VDDRHF) for mixed noise suppression and fine-details preservation in color images. The Implementation was done, based on FPGA HW/SW validation using efficient hardware optimizations and non linear function approximations. The validation using FPGA board confirms the color image quality preservation...
Particle filter has been considered as great advancement for radar tracking in nonlinear and non-Gaussian scenarios. But the huge computation and complexity limited its application in real-time systems. In this paper, we improve the architectures of sampling importance resampling particle filter (SIRF) in FPGA on the Xilinx VIRTEX-5 platform and then apply it to the bearings-only tracking system....
Reduction circuits are used to reduce rows of floating point values to single values. Binary floating point operators often have deep pipelines, which may cause hazards when many consecutive rows have to be reduced. We present an algorithm by which any number of consecutive rows of arbitrary lengths can be reduced by a pipelined commutative and associative binary operator in an efficient manner. The...
The modulated complex lapped transform (MCLT) is a 2times oversampled DFT filter bank. The MCLT has showed to be a good selection in audio compression and watermarking systems. It has been demonstrated that a length-M MCLT can be mapped to a length-2M fast Fourier transform plus M butterfly-like stages without data shuffling, therefore, the MCLT is appropriate for efficient hardware implementations...
A new lossy compression algorithm for RF ultrasound signals (A-scan) is presented, which stores only the largest variations of the original signal. The largest variation (LAVA) algorithm is a two-step, constant bit-rate (CBR) algorithm, using only simple addition/subtraction operations, which is very suitable for FPGA implementation. The algorithm is targeted for automated ultrasonic testing (AUT)...
This paper presents an efficient technique for addressing in radix-2 FFT architectures. The novel addressing organization provides parallel load and store of the data involved in a radix-2 butterfly computation. The addressing scheme is based on a permutation of the FFT data, which leads to the minimization of the address generating circuit and the butterfly processor control. The paper proves the...
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