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This paper presents a design for an interrogator for a new class of passive wireless sensors. The sensors are intended for deeply embedded structural health monitoring applications. As such, the interrogator must both transmit a signal to elicit a response from the sensor and be able to monitor that response. The interrogator considered transmits in the 2.40-2.48 GHz ISM band and monitors the 2nd...
Filtering data in real-time requires dedicated hardware to meet demanding time requirements. If the statistics of the signal are not known, then adaptive filtering algorithms can be implemented to estimate the signals statistics iteratively. This paper aims to combine efficient filter structures with optimized code to create a system-on-chip (SOC) solution for various adaptive filtering problems specially...
Edge of image is one of the most fundamental and significant features. Edge detection is always one of the classical studying projects of computer vision and image processing field. It is the first step of image analysis and understanding. With the continuous improvement of remote sensing image, especially the appearance of Digital Aerial Image, edge detection is necessary step to extract information...
This paper describes the design and testing of the optimal type-2 fuzzy controller obtained using genetic algorithms (GA) for the optimization of triangular and trapezoidal membership functions of a fuzzy system, for hardware representations such as the Field Programmable Gate Array (FPGA). The GA uses only certain points of the membership functions, the fuzzy rules are not changed, with the purpose...
Aiming at the requirements of real time signal processing, a cut-off frequency of 100 KHz, 16-tap direct form FIR linear-phase low-pass filter using Kaiser Window function was designed out based on DSP Builder system modeling approach. The signal waveforms in time domain and frequency domain before and after filtering were analyzed. Ultimately, a highest response frequency of 61.71MHz high-speed FIR...
Edge detection is one of the key stages in image processing and object recognition. The Canny edge detector is one of the most widely-used edge detection algorithms due to its good performance. In this paper, we present a distributed Canny edge detection algorithm that results in significantly reduced memory requirements, decreased latency and increased throughput with no loss in edge detection performance...
Two hardware architectures are developed via an improved parameterized efficient FPGA implementation method for parallel 1-D real-time signal filtering algorithms to provide higher performance per Watt and minimum logic area at maximum frequency. This improvement is evidently manifested rapid system-level abstraction FPGA prototyping and optimized speed, area and power, targeting Virtex-6xc6vlX130Tl-1lff1156...
Field Oriented Control (FOC) Permanent Magnet Synchronous Motor (PMSM) is mostly used as it provides superior torque to inertia ratio, high controllability and greater power density amongst all the servo drives. However, expensive computing elements are required for the driver circuits which are the key factor of determining the overall performance of FOC-PMSM drives. In addition, an exact direct...
This paper presents a new design of 2D median filter. The filter implements a simple conditional filtering technique that executes fewer computations than related formulations while achieving superior image quality. Experimental FPGA implementations of the proposed filtering scheme for window sizes of (3×3) and (5×5) are very compact, fast and consume low-power.
We report a two-dimensional (2D) pixel block scanning architecture for image segmentation by segment growing. This architecture can optimize processing speed, power consumption, and circuit area by modifying size and shape of the pixel block. Real-time processing can be maintained by using additional the two important techniques of (i) boundary-scan of the grown segment only, (ii) continued block-internal...
The trigonometric functions sine and cosine have found numerous applications in various areas. For Satellites, the smallest category envisioned is the “femptosat” which would weigh less than one-tenth of a kilogram, a satellite that would handle very simple missions and would be implemented on a single chip. One of the elementary things required in these satellites is the Satellite Attitude Determination...
Fast Fourier Transform (FFT) is an efficient algorithm to compute the Discrete Fourier Transform (DFT). In many applications the input data are purely real-time, and efficient FFT can satisfy the situation. FFT algorithm based on complex sequence is an improved algorithm of primary FFT. This paper studies how efficient FFT algorithm is implemented on the basis of Field Programmable Gate Array (FPGA)...
In this work, we propose a design and (FPGA) implementation of architecture of an entirely parallel SISO decoder for turbo decoding of the product codes with low complexity for high data rate applications. As an example we study a soft input/output decision decoding for the BCH (31, 26, 3) code. The VHDL design and synthesis of such architecture showed that the use of the structure combining the sub-blocks...
In wireless communication, equalization is an effective technology to change channel characteristics and reduce the Inter-Symbol Interference (ISI). Based on analyzing the LMS algorithm, the application of this algorithm in channel equalizer is studied. A Channel Equalizer based on LMS algorithm is implemented using Xilinx System Generator for DSP develop software. This implementation method is a...
This paper presents a method for fast, parallel matrix implementation of an integer division algorithm inside FPGA that can be used for real-time control systems. An essential improvement over the known matrix structure was made, with all the matrix lines having the same width, which leads to equal and reduced propagation time. The alignment was also improved by reducing one algorithm step and eliminating...
FPGAs have been mainly used for designing of synchronous controllers. However, it is difficult to design asynchronous controllers on them because the circuit may suffer from hazard problems. This paper presents a method that implements a class of asynchronous controllers on FPGAs which are based on Look-Up Table (LUT) architectures. Asynchronous controllers specification used in heterogeneous (synchronous...
The second round of the NIST-run public competition is underway to find a new hash algorithm(s) for inclusion in the NIST Secure Hash Standard (SHA-3). This paper presents the full implementations of all of the second round candidates in hardware with all of their variants. In order to determine their computational efficiency, an important aspect in NIST's round two evaluation criteria, this paper...
In this work the image is segmented effectively based on texture feature by reducing the noise. For effective image segmentation Expectation-Maximization (EM) algorithm based on Gabor filter is used. The EM algorithm is applied on 2D Ultrasonic image of uterus and tested. The Gabor function has been recognized by its multiresolution properties and the precision of locating the texture features in...
Many multiphase interleaved DC/DC converter requires current sharing with average current control. Conventional current sharing schemes are based on sensing each phase current to provide the current information to the current control loop. Such schemes have drawback of affection by the sensing accuracy of each phase. Additionally, the switch actions in multiphase interleaved DC/DC converter lead to...
In this work, FPGA implementation of the compression function for four of the second round candidates of the SHA-3 competition are presented. All implementations w ere performed using the same technology and optimization techniques to present a fair comparison between the candidates. Achieved results are compared with similar implementations to provide a comprehensive comparison of candidates performance...
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