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The developed Hardware-in-the-Loop (HIL) Simulation was used to evaluate the performance of the electrical machinery driver systems in some cases which are very difficult or impossible to be tested in laboratory environment. By using this simulation environment, Embedded Control Systems (ECS) can easily be tested in a practically, cheaply and unhazardous way. In this study, we have developed a novel...
A high-performance computation platform based on field-programmable gate arrays targets nuclear and particle physics experiment applications. The system can be constructed or scaled into a supercomputer-equivalent size for detector data processing by inserting compute nodes into advanced telecommunications computing architecture (ATCA) crates. Among the case study results are that one ATCA crate can...
Synchronous dataflow (SDF) is an ubiquitous dataflow model of computation that has been studied extensively for efficient simulation and software synthesis of DSP applications. In recent years, parameterized SDF (PSDF) has evolved as a useful framework for modeling SDF graphs in which arbitrary parameters can be changed dynamically. However, the potential to enable efficient hardware synthesis has...
Real-time wireless channel simulators are necessary for radio prototyping. Doppler filter is one of the basic building blocks in correlation-based channel simulators. Enormous computational complexity of channel models for new wireless standards like MIMOs prohibit their software realizations (which have traditionally been the case). In first part of this work, we dimension and compare two alternative...
A low-complexity hardware implementation method is proposed for discrete-time frequency-selective Rayleigh fading channels. The proposed method first employs the sum-of-sinusoids method to generate multiple independent flat fading channel responses, then utilizes a simple weight-delay-sum filtering method to incorporate the fractionally-delayed multipath rays into inter-tap correlated tap gains. It...
We have constructed a FPGA-based ldquoearly neural circuit simulatorrdquo to model the first two stages of stimulus encoding and processing in the rat whisker system. Rats use tactile input from their whiskers to extract object features such as size and shape. We use the simulator to examine the plausibility of the hypothesis that neural circuits in the ratpsilas brain compute gradients of radial...
We present PHAST, a pipelined hardware accelerated explicit-state model checker. The algorithms and methodologies used to perform the state checking in PHAST are based on the Mur?? verifier, developed at Stanford University. Mur?? has been used to verify hardware and protocols, cache coherency protocols in particular. Mur?? is used in industry due to its success in finding errors in real designs....
Systolic arrays may prove ideal structures for the representation and the mapping of many applications concerning various numerical and non-numerical scientific applications. Especially, some formulation of Dynamic Programming (DP) - a commonly used technique for solving a wide variety of discrete optimization problems, such as scheduling, string-editing, packaging, and inventory management can be...
This paper presents the real-time hardware implementation of three-phase induction motor modelling, using a Field Programmable Gate Array (FPGA) device, in order to use in real-time simulations. The proposed model runs directly in hardware by using FPGA technology and it allows a remarkable speed up in comparison with conventional models which based only software. Such a model was developed with the...
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