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We report a two-dimensional (2D) pixel block scanning architecture for image segmentation by segment growing. This architecture can optimize processing speed, power consumption, and circuit area by modifying size and shape of the pixel block. Real-time processing can be maintained by using additional the two important techniques of (i) boundary-scan of the grown segment only, (ii) continued block-internal...
This paper describes an FPGA implementation which features a hardware-oriented Scale Invariant Feature Transform (SIFT) algorithm, a scalable architecture with high-speed mode and high-accuracy mode, and highly parallel datapath modules. The proposed FPGA implementation can generate a SIFT descriptor vector with 50 MHz for VGA resolution video (640 × 480 pixels) at 56 frames per second (fps). Our...
A fast algorithm of extracting laser line is proposed for real-time image processing in 3DLCS and is compared with the former algorithm. First of all, the threshold S(T) of the laser stripe is computed by host computer unnecessarily in real time. Second the laser stripe is determined in real time. At last the central line of the laser stripe is detected by templates in real time. The fast algorithm...
This paper presents the architecture and FPGA implementation of a video processor for detection and correction of specular reflections in endoscopic images by using an inpainting algorithm. Stream processing and parallelism are used to exceed real-time performance on NTSC format video without the need for an external memory. The system was implemented in a XC2VP30 FPGA and uses 91% of available slices...
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