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In this invited paper, both binary and nonbinary LDPC codes suitable for optical transmission systems are described. The corresponding FPGA implementation has been discussed as well. The use of adaptive LDPC coding to deal with time-varying optical channel conditions is described as well.
This paper presents a lossless, low latency, low power dissipation compression for long-term wearable ECG monitor to reduce the amount of data, avoiding costly unnecessary wireless data transmission to extend battery life. In this research, we introduce an approach base on run-length coding, which compresses ECG signal by preforming duplicate data encoding by using the characteristics of ECG signal...
Large-width multiplier is one of the most important computing units, such as for encrypt chip basing on RSA algorithm. In this paper, a circuit structure which is the optimized multiplier with innovative Booth algorithm is put forward. We proposed an innovative algorithm that can be generalized to N-bit multiplier design. Meanwhile, comparing to the original Booth multiplier, it speeds up the computation...
The paper describes basic methods of data compression without loss and analyzes their advantages and disadvantages. There is a hardware implementation on FPGA of compression algorithm for stream processing of information. This algorithm can be used in applications related to telecommunications networks of distributed control systems.
A Pipe-line based High speed Image Coding Architecture (PL-HICA) was proposed in this paper, which was designed to implement wavelet based image coding algorithm. PL-HICA contains 6 processing elements, which are a Slice Element, two 2D-5/3DWT Elements, a 2D-DWT&Predict Elements, a Run-length & Exp-Golomb coding Element and a Package Element. The PL-HICA features low complexity, low hardware...
In this paper, we present a high performance and low power hardware architecture for real-time implementation of Context Adaptive Variable Length Coding (CAVLC) algorithm used in H.264 / MPEG4 Part 10 video coding standard. This hardware is designed to be used as part of a complete low power H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL...
This paper discusses the synthesis and implementation of various scheduling algorithms for Network-on-Chip communication. Traditionally these scheduling algorithms were implemented on ASIC platforms generally for shared bus based interconnection systems. In this paper we carry a comparative analysis by synthesizing and implementing various scheduling algorithms for configuring the crossbar in input...
A very efficient algorithm and hardware architecture for code block segmentation used on LTE-Advanced channel coding physical layer (PHY) is presented in this paper. Code block segmentation is a generic procedure which is commonly applied before turbo encoding. Its main function is to fragment a large transport block into smaller code blocks. This approach reduces memory requirements of the turbo...
To reduce external memory access latency and power in embedded applications, frequently re-used data is identified and buffered in on-chip memory. This paper presents an approach to on-chip memory sub-system architecture for data dependent image processing algorithm. The proposed memory architecture is capable of re-using the data and reduces the external memory access latency. It is implemented and...
In this paper, we propose a novel architecture for implementing the Goertzel algorithm for exon prediction. Compared to previous designs, this one does not require multiple retransmissions which increase the number of clock cycles required to complete an operation. The proposed design is able to produce a new output on every clock cycle, which improves the throughput by roughly thirty times. The system...
PLCs have been the first choice for automation engineers for fast, reliable and robust implementation of their control algorithms for many years. Recently, with the introduction of advanced MEMS sensors and actuators and the penetration of new technologies in many diverse everyday tasks, with complicated control mechanisms and advanced calculations, it has been made clear that traditional PLCs need...
This paper presents a novel hardware architecture for the Goertzel algorithm used in exon prediction. It also describes the rapid-prototyping methodology for the implementation of this system. The approach used in this work relies on a top-down philosophy which starts from a MATLAB model and ends in a hardware implementation on FPGA. The design was implemented on a PCI FPGA board installed in the...
Finding an optimum function is not only a theoretical mathematical problem but also a particular engineering problem. Many aspects in the electrical and electronics field (by example: image processing, filter matching, optimization of network parameters, resources allocation) can be solved by finding a target function and his minimum or maximum. For such problems, usually an analytical solution is...
Through improving the existing coding algorithms, this paper presents a new coding algorithm, which reduces power dissipation in the way of reducing the number of partial product. Because the main operation of the multiplier is the sum of partial products, therefore, the reduction of the number of partial product can decrease the number of adder in multiplier, so the power dissipation can be decreased...
FSM-based and microcode-based controllers are two widely known techniques used for memory built-in self test (MBIST). FSM-based controller is commonly the hardwired BIST whilst microcode-based controller is a programmable memory BIST (P-MBIST) controller. The P-MBIST is popular because of their flexibility of programming new test algorithms. Recently, the FSM-based memory BIST has evolved from hardwired...
Dynamic Voltage Scaling (DVS) has been a key technique in exploiting the hardware characteristics of processors to reduce energy dissipation by lowering the supply voltage and operating frequency. As applications become increasingly sophisticated and processing power increases, the most serious limitation on these devices is the available battery life. This paper presents a low-power FPGA system with...
Data encryption process can easily be quite complicated and usually requires significant computation time and power despite significant simplifications. This paper discusses about pipelined and non-pipelined implementation of one of the most commonly used symmetric encryption algorithm, Data Encryption Standard (DES). The platform used for this matter is, Xilinx new high performance silicon foundation,...
Traditionally, computational systems based on FPGA technology take advantage of the device's configurable resources in order to adapt to different working scenarios. This paper presents a communication system developed in VHDL, targeting an anti-fuse programmable once FPGA device, that adapts to environmental conditions, with no use of reconfigurable technology. The design and implementation of the...
The nesting of 3-dimensional parts problem is important for practical applications. In the field of VLSI design, the nesting of 3-dimensional parts problem arises from both the packing of the 3-D integrated circuits and the task schedule of FPGA design. In this paper, we propose a novel floor plan representation, named 3-Dimensional Corner Layout List to encode the topology of the 3-D nesting. Based...
Internet Protocol Security (generally shortened to IPSec) is a framework of open standards that provides data confidentiality, data integrity, and data authentication between participating peers at the IP layer. The Data Encryption Standard(DES) is used to encrypt and decrypt packet data at IP layer; it turns clear text into cipher text via an encryption algorithm. The decryption algorithm on the...
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