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It has been demonstrated that, in a 64-b carry look-ahead adder, the use of conventional half-micron BiCMOS circuits under a 3.6-V power supply gives 40% faster delay than the CMOS design. Up to 85% improvement is obtained with the new multiemitter BiCMOS circuit. A complete logic circuit family with the multiemitter concept is described, showing a maximum benefit on gates with a high number of inputs
The authors present a general appraisal of voltage-dependent speed degradation for three kinds of BiCMOS logic circuits from the viewpoints of (1) essential delays without parasitic capacitances, (2) practical delays with parasitics, (3) full-swing (power to ground) mode operation, and (4) partial-swing operation. The essential delay times of the three circuits are analytically derived and effects...
It has been demonstrated that full-swing complementary MOS/bipolar logic (FS-CMBL) circuits utilizing a push-pull emitter-follower driver and base-emitter shunting to achieve full swing are potentially advantageous for scaled BiCMOS technologies. In these circuits, delay and power consumption depend on characteristics of the base-to-base clamping diode, parasitic capacitances at the two base nodes,...
A two-input, two-output element switch for use in future ATM (asynchronous transfer mode) switching systems for buffered banyan networks with CASO (contents associated output) buffers has been realized in 0.8-μm BiCMOS technology. Three key features of the element switch architecture are CASO buffers to increase the throughput, SCDB (synchronization in clocked dual-port buffer) to make asynchronous...
A 7-ns, 1 M×1/256 K×4 BiCMOS ECL (emitter coupled logic) SRAM with program-free redundancy is described. To obtain the fast address access time and low power consumption, an improved ECL buffer and two-stage sensing scheme were adopted. The SRAM was fabricated with a 0.8-μm double-poly-Si double-metal BiCMOS technology. The RAM has an ECL 10 K interface and operates at a...
A 1-Mb ECL (emitter coupled logic) I/O SRAM which has been fabricated using 0.8-μm BiCMOS technology is described. The die is configurable to four different organizations (1 Mb×1, 1 Mb×1 with differential output, 512 K×2 with differential output, and 256 K×4) by way of bonding options. The device, with a die size of 240 mil×475 mil, has a typical...
The authors describe a low-power comparator circuit which is especially useful for on-chip cache-TAG memories. A novel TAG memory comparator circuit scheme, called a current-mode column comparator (CMCC) scheme, is proposed, and the low-power nature of the CMCC without degraded accessing speed is described. An experimental 128-entry by 32-b TAG-memory test chip was fabricated using 0.5-μm BiCMOS...
A BiCMOS technology is described that is built on an optimized 3.3-V 0.5-μm CMOS base process. A high-performance single-polysilicon npn transistor with a cutoff frequency of 15 GHz is integrated using CMOS-compatible heat cycles. Novel level-shifted BiCMOS circuit techniques are employed to allow the bipolar devices to operate at a higher voltage (4.1 V) without performance degradation while...
A BiCMOS structure called SST-BiCMOS is proposed. In this structure, a high-performance emitter-base self-aligned bipolar technology using double polysilicon layers called SST and a submicron-gate-length lightly doped-drain MOS technology are used. This structure was used to realize high-performance BiCMOS technology with a cutoff frequency of 20 GHz, an NPN transistor, a propagation delay time of...
A unified delay model is presented that predicts BiCMOS gate delay for both long- and short-channel MOSFETs, in low-level and high-level injection in the bipolar junction transistors (BJTs), for 5 V and reduced supply and over a wide range of circuit parameter variation. The model is applied to devise circuit and device design strategies to optimize gate performance at 5 V and at scaled supply voltage...
An advanced BiCMOS technology (ABiC IV), developed by integration of high-performance CMOS devices with a state of the art bipolar process, is presented. The core bipolar process is the fourth generation of the advanced single poly emitter coupled technology (ASPECT). Gate delays of 47 psec, 110 psec and 120 psec have been achieved for unloaded ECL, CMOS and BiCMOS gates, respectively. In addition...
The deficiencies of BiCMOS logic are analyzed, and the addition of a high-performance vertical pnp to the BiCMOS technology, henceforth called complementary BiCMOS technology, is considered as a solution. It is suggested that density problems associated with BiCMOS logic can be alleviated by replacing the conventional BiCMOS logic circuit, i.e. the `totem-pole' circuit, with a simpler complementary...
A method of high-performance and simple fully complementary bipolar MOS (FCBiMOS) process integration is proposed that is compatible with a conventional 0.5-μm CMOS and BiCMOS process. This process is based on two key technologies. One is a high-dose boron MeV ion implantation combined with an epitaxial wafer. The other is rapid thermal processing (RTP) for high current gain. It has been confirmed...
To realize high performance mixed analog and digital ASICs, a novel CBi-CMOS technology is proposed. This technology, called DIIP (double-implanted and isolated P-well) CBi-CMOS technology, is characterized by a structure with vertical NPN, PNP and CMOS structures on the same chip. In this structure, a vertical PNP transistor and NMOS transistor are fabricated in a P-well, which is isolated from the...
A RAM which uses circuit techniques and architectural innovation to achieve the performance demanded by today's systems is described. An input buffer/level translator, a current sense amplifier, and a high-speed architecture are used in this RAM to achieve the 5-ns access time along with the 0.6-μm BiCMOS technology. The chip is organized as 128 K-words×8-b wide using a 4T2R memory...
Deep submicrometer CMOS devices having a novel well structure using thin epitaxy over a buried n+ layer, a p-type substrate, and trench isolation are proposed. Good isolation characteristics and high latchup immunity are obtained. The thin epitaxial layer, which is necessary for on-chip high-performance bipolar devices, lowers the voltage tolerance of the parasitic vertical bipolar, and causes a new...
The 10-b, 10 MHz BiCMOS A/D (analog-to-digital) converter with a triple-stage conversion scheme, combined with two novel conversion schemes, the dynamic sliding reference method and the triangular interpolation method, has been developed. This novel conversion scheme and BiCMOS circuit technology reduce element counts of bipolar transistors to only 2000. A small active area of 2.5×2.7 mm...
A phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is employed to generate an internal clock synchronized to a reference clock from outside a chip, has been developed using 1.0-μm BiCMOS technology. In order to obtain a very wide operation bandwidth, it is proposed that the PCG included a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation...
A fast-access intermediate supply voltage level BiCMOS SRAM (ISVOL) architecture is proposed for advancing circuit technology to megabit-level SRAMs using low-submicron MOSFETs. To verify this concept's effectiveness, a 256-kb SRAM, with a typical access time of 5 ns, is evaluated and reported. The access time dependence of the supply voltage is shown. This architecture can suppress the access time...
A BiCMOS gate array with gate delay of 350 ps has been realized by 0.8-μm BiCMOS technology. Minimum gate delay and cell area have been achieved with a shared bipolar cell structure. The gate delay is almost equivalent to that of a 0.5-μm pure CMOS gate array. The cell-area increase is to only 25% compared with a 0.8-μm pure CMOS cell. I/O cells can interface with CMOS, TTL (transistor-transistor...
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