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An advanced BiCMOS technology (ABiC IV), developed by integration of high-performance CMOS devices with a state of the art bipolar process, is presented. The core bipolar process is the fourth generation of the advanced single poly emitter coupled technology (ASPECT). Gate delays of 47 psec, 110 psec and 120 psec have been achieved for unloaded ECL, CMOS and BiCMOS gates, respectively. In addition...
A BiCMOS gate array in 0.8-μm technology has been developed with gate delays of 360 ps with a 0.4 pF load. A compact base cell (750 μm2/gate) has been designed with full bipolar drive capability. A 160 K-gate array has been built on a 1.14 cm square chip with ECL (emitter-coupled logic) I/O capability. Placing and routing in three levels of metal provide array utilization up to 92%....
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