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A unified delay model is presented that predicts BiCMOS gate delay for both long- and short-channel MOSFETs, in low-level and high-level injection in the bipolar junction transistors (BJTs), for 5 V and reduced supply and over a wide range of circuit parameter variation. The model is applied to devise circuit and device design strategies to optimize gate performance at 5 V and at scaled supply voltage...
The authors describe a submicron BiMOS process in which the lateral BJTs (bipolar junction transistors) are so similar to the MOSFETs that no extra process steps are needed. A lateral npn BJT with beta higher than 1000 has been demonstrated. A lateral pnp BJT with high cutoff frequency has been demonstrated, provided the parasitic capacitances are minimized. It is believed that this lateral BJT can...
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