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An architecture that improves serial I/O operation speed, reduces layout area, and permits simple control is presented. The architecture features a high-speed, simple configuration, an easy controllable data shifter, and an high-speed redundancy circuit. With this architecture, a 4-Mb field memory with 100-MHz serial access capability has been developed. The process technology used is 1.0 μm...
A novel two-transistor DRAM cell technology is introduced which uses a unique clamped bit line, unbalanced-gain sense amplifier. The 2T cell topology offers nondestructive readout of the cell state and high-speed operation. The speed of the sense amplifier is independent of bit-line capacitance, and the bit lines of the new topology are insensitive to noise voltage coupling. The memory exhibits access...
A 7-ns, 1 M×1/256 K×4 BiCMOS ECL (emitter coupled logic) SRAM with program-free redundancy is described. To obtain the fast address access time and low power consumption, an improved ECL buffer and two-stage sensing scheme were adopted. The SRAM was fabricated with a 0.8-μm double-poly-Si double-metal BiCMOS technology. The RAM has an ECL 10 K interface and operates at a...
Progress in OEIC (optoelectronic integrated-circuit) technologies is briefly reviewed, and the feasibility of optically integrated ULSI is examined. It is concluded that an overall delay time of 0.1-0.2 ns will be achievable for a bus line in ULSI using optical interconnections, which is more than one order of magnitude faster than the conventional metal wire bus line. Future prospects in optoelectronics...
A 1-Mb ECL (emitter coupled logic) I/O SRAM which has been fabricated using 0.8-μm BiCMOS technology is described. The die is configurable to four different organizations (1 Mb×1, 1 Mb×1 with differential output, 512 K×2 with differential output, and 256 K×4) by way of bonding options. The device, with a die size of 240 mil×475 mil, has a typical...
New high-density DRAM core designs based on a new divided bitline sensing principle are proposed and their performance is estimated. These designs can achieve a high-density memory cell array and can also overcome problems of the scaled memory array. These designs are promising candidates for 64-Mb DRAM and beyond
A low-voltage circuit technology for 1.5-V, 64-Mb DRAMs designed to achieve a reasonable speed performance projected from existing trends is described. The DRAM has been deigned using novel low-voltage circuits. An RAS access time of 50 ns has been obtained with power dissipation as low as 44 mW. These results show that a low-voltage battery-operated DRAM is a promising target for the future
A fully planarized two-level-metal structure has been successfully fabricated at 0.5 μm groundrules with the use of X-ray lithography at all processing levels. A 0.5-μm minimum feature size was required for all levels, including the second-level metal. Planarized PECVD oxide and PECVD nitride were employed as dual dielectric layers below M1 and M2. Chemical vapor deposition (CVD) W studs...
A description is given of a newly developed selective interlayer dielectrics formation technology to realize completely planarized multilevel interconnections. The technology uses liquid phase deposition (LPD) at extremely low temperature (~40°C). This technology has the capability to realize high density VLSIs such as logic devices beyond 100-kgate and memory devices beyond 16-Mb because...
A stacked-CMOS SRAM cell with a polysilicon p-channel thin-film transistor (TFT) load that has been attracting much attention as a high-density and low-standby-current SRAM is considered. The authors demonstrate a high-performance stacked-CMOS SRAM cell with remarkably improved polysilicon p-channel TFT load characteristics: a leakage-current of 0.07 pA/μm, and an on/off ratio of 105 at the...
The authors propose a buried bit-line (BBL) stacked capacitor cell structure for high-density dynamic random access memories (DRAMs). The cell area can be reduced to as small as 8.7<e1>F</e1>2, where <e1>F</e1> is the lithographic feature size. A 2.25-μm2 cell area is achieved using a 0.51-μm feature size. A 1.4-μm2 cell area is attainable using a 0.4-μm...
A RAM which uses circuit techniques and architectural innovation to achieve the performance demanded by today's systems is described. An input buffer/level translator, a current sense amplifier, and a high-speed architecture are used in this RAM to achieve the 5-ns access time along with the 0.6-μm BiCMOS technology. The chip is organized as 128 K-words×8-b wide using a 4T2R memory...
Thin-film transistor (TFT) cell technology has been proposed for high-density SRAM cells. It was demonstrated that when utilizing this technology both low standby current and high cell stability are obtained simultaneously without increasing cell size. TFT characteristics required for 4-Mb SRAMs are discussed, and it is noted that improvements in packing density while maintaining low standby current...
The technology used to fabricate high-speed and low-power 64-Mb DRAMs (dynamic random access memories) is described. The memory cell developed is a high-storage capacitance bit-line shielded stacked capacitor (STC) cell in which the storage capacitor is formed over the bit-line and a cylindrical storage node structure is used for low-voltage memory operation. The main features of the technology are...
A high performance 16-Mb DRAM technology is presented. The key issues that must be considered to achieve high yield and reduced cost are described. Technology elements include: deep trench capacitor node with thick oxide collar for improved packing density, variable-size shallow trench isolation (STI) for device performance and ease of integration, polysilicon surface strap to connect the capacitor...
An SRAM cell structure using stacked double-gated, self-aligned polysilicon PMOS thin-film transistors (TFT) is described. This memory cell has been realized in a half-micron, triple-poly, double-metal CMOS process; the cell area is 22.32 μm2, adequate for 4-Mb SRAMs. The main features are: (i) self-aligned structure to precisely define the TFT channel, (ii) TFT drive current enhancement by...
An 8-ns serial access time has been realized in a 4-Mb static RAM with newly proposed circuits (hierarchical shift registers and look-ahead circuits) which can access up to 4 Mb. This memory realizes a 125-MHz fast serial READ/WRITE operation suitable for ultra-high-speed memory systems such as image-processing systems, high-speed testing systems, and supercomputers. This function is also beneficial...
A major hurdle in VLSI/ULSI technology has been the inability to grow ultrathin oxides with low defect and interface trap densities and to generate a planar stress-free silicon/silicon-dioxide (Si/SiO/sub 2/) interface. The authors describe the fabrication of thin multilayered stacked SiO/sub 2/ structure with such qualities. A huge improvement in the quality of these stacked oxides has been achieved...
A novel three-dimensional buried trench (BT) memory cell, suitable for DRAM (dynamic random access memories) of 64 Mb or beyond, has been demonstrated. It uses a novel self-aligned-epitaxy-over-trench (SEOT) technology which allows the fabrication of the cell horizontal access transistor in bulk material epitaxially grown over the trench capacitor. The via connection between the access transistor...
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