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The operation of a ferroelectric memory cell for nonvolatile random access memory (NVRAM) applications is described. Because ferroelectric polarization reversal only occurs during store/recall but not DRAM read/write, ferroelectric fatigue is not a serious endurance problem. In the worst case, the effective silicon dioxide thickness of the unoptimized film studied here is less than 15 Å...
The authors propose a buried bit-line (BBL) stacked capacitor cell structure for high-density dynamic random access memories (DRAMs). The cell area can be reduced to as small as 8.7<e1>F</e1>2, where <e1>F</e1> is the lithographic feature size. A 2.25-μm2 cell area is achieved using a 0.51-μm feature size. A 1.4-μm2 cell area is attainable using a 0.4-μm...
The inverted dependence of the soft-error rate (SER) on the cycle time in static RAMs with high resistive load cells is described. The inverted dependence is observed in the SRAM with a PMOS bit-line load. At a cycle time of 100 ns, the SER is reduced by 1.5 orders of magnitude, compared with that of the SRAM with NMOS bit-line load. The mechanism is explained with reference to the time constant of...
The technology used to fabricate high-speed and low-power 64-Mb DRAMs (dynamic random access memories) is described. The memory cell developed is a high-storage capacitance bit-line shielded stacked capacitor (STC) cell in which the storage capacitor is formed over the bit-line and a cylindrical storage node structure is used for low-voltage memory operation. The main features of the technology are...
A high performance 16-Mb DRAM technology is presented. The key issues that must be considered to achieve high yield and reduced cost are described. Technology elements include: deep trench capacitor node with thick oxide collar for improved packing density, variable-size shallow trench isolation (STI) for device performance and ease of integration, polysilicon surface strap to connect the capacitor...
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