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An EPROM cell structure is described that uses folded word lines with double Al layers. Cell characteristics are optimized to obtain high-speed access. The data retention reliability and erasability are studied, focused on a 2Al metallization process. The feasibility of the technology has been confirmed by a 1-Mb CMOS EPROM device which shows 16 ns access time and extremely high data retention reliability...
Thin-film transistor (TFT) cell technology has been proposed for high-density SRAM cells. It was demonstrated that when utilizing this technology both low standby current and high cell stability are obtained simultaneously without increasing cell size. TFT characteristics required for 4-Mb SRAMs are discussed, and it is noted that improvements in packing density while maintaining low standby current...
A novel EPROM (erasable programmable read-only memory) cell structure with asymmetrically doped source and drain junction suitable for virtual ground array architecture is described. The asymmetric cell nature eliminates a write disturbance of the adjacent cell in the write mode. In the read mode, the cell provides higher read current and substantial soft-write lifetime as a result of the selection...
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