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The authors propose a buried bit-line (BBL) stacked capacitor cell structure for high-density dynamic random access memories (DRAMs). The cell area can be reduced to as small as 8.7<e1>F</e1>2, where <e1>F</e1> is the lithographic feature size. A 2.25-μm2 cell area is achieved using a 0.51-μm feature size. A 1.4-μm2 cell area is attainable using a 0.4-μm...
An SRAM cell structure using stacked double-gated, self-aligned polysilicon PMOS thin-film transistors (TFT) is described. This memory cell has been realized in a half-micron, triple-poly, double-metal CMOS process; the cell area is 22.32 μm2, adequate for 4-Mb SRAMs. The main features are: (i) self-aligned structure to precisely define the TFT channel, (ii) TFT drive current enhancement by...
A 25- mu m/sup 2/ poly-Si PMOS load SRAM (static random access memory) cell, called a PPL cell, has been developed. The cell has been excellent retention characteristics, high soft-error immunity, and low standby power. These advantages are achieved using poly-Si PMOS loads and cross-coupled stacked capacitors formed between the NMOS and the stacked poly-Si PMOS. A large poly-Si PMOS ON current lowers...
A contactless cell array technology has been developed for a single-power-supply 5V-only CMOS flash EEPROM (electrically erasable programmable read-only memory). The technology's suitability for VLSI memories has been demonstrated by a 256-kb flash EEPROM test vehicle. This low-current approach has been realized with cell area and cost comparable to those of the recently reported dual-power-supply...
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