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This paper presents a novel bias circuit for achieving process and temperature invariant resistor using a MOSFET operating in triode region. The proposed circuit comprises of an enhanced process tracking circuit and complementary to absolute temperature (CTAT) voltage generators. The proposed circuit has been designed and optimized in 180nm mixed-mode CMOS technology. Exhaustive Montecarlo simulations...
We report our results on pulse-forming-line (PFL)-based CMOS pulse generator studies. Through simulations, we clarify the effects of PFL length, switch speed, and switch resistance on the output pulses. We model and analyze CMOS pulse generators with on-chip transmission lines (TLs) as PFLs and CMOS transistors as switches. In a 0.13- m CMOS process with a 500- m long PFL, post-layout simulations...
In-place diagnosis of off-chip power delivery resonance is demonstrated with on-chip waveform capturer and power delivery network (PDN) exciter that were prototyped in a 65 nm CMOS technology. Oscillatory waveforms are captured after the excitation of PDN, from which an LCR lumped equivalent circuit of PDN seen by on-chip circuits is algorithmically derived. The consistency of component values is...
A monolithic step-up dc-dc converter with on-chip spiral inductors is designed and simulated to determine its feasibility for low-power portable applications. The converter is operated at a relatively high frequency of 600 MHz to reduce passive component sizes. Quality factor limitations of on-chip inductors are mitigated without increasing the area by implementing multiple spirals on different layers...
A new partially-thickened local (PTL)-interconnect structure with an extremely low resistance is developed for the 40 nm-node low-power CMOS device to boost the RF performance. The PTL-interconnect is featured by the Cu dual-damascene (DD) interconnect combined with the slit-contact (SLICT) in the low-k pre-metal-dielectrics (PMD, k=3.1), accomplishing 50% reduction in the resistance of metal-1 (M1),...
In this paper, a simple wideband circuit model for on-chip spiral inductors is presented. The model shows excellent agreement with measured data mostly within 4.91% across a variety of inductor geometries up to 20 GHz. The proposed model has been verified with measured results of inductors fabricated in 0.13 μm CMOS process. The inductors have two dimensions: turn and inner radius. The new model accurately...
An off-chip load driving low drop-out regulator with high power-supply rejection is proposed in this paper. The 1.2-V regulator uses adaptive frequency compensation and is stable at all load currents. A power-supply rejection of 70 dB with load and line regulation figures of under 2 mV and 10 mV for 1-350 mA and 2.1-3.6 V load current and power supply variations were measured on a 65-nm CMOS prototype...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
Three dimensional memory systems has been argued as a potential pathway in solving the ever growing difference between comparative speeds of CPU and memory systems. In this paper, we describe a three-tier, three-dimensional SRAM macro that has been designed and fabricated in a 0.18 um FD-SOI CMOS technology. 3D stacking is found to improve wire latency as compared to planar memory structure although...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled CMOS technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
Ultra Thin Body Si-On-ONO (UTB SOONO) transistors with ultra thin spacer are successfully demonstrated and evaluated. They have shown increased driving current more than 30% compared with conventional UTB SOONO transistors with thick spacer due to reduced source/drain resistance without short channel effect degradation by using thin spacer. In this paper, it is shown that thin spacer technology is...
A novel way of manufacturing an on-chip transformer that produces high inductance ratio (LSec/LPri > 30) with excellent area efficiency is presented. This technique uses an electrical all-round coupling effect of a conductor A (primary coil), having large effective width, and a densely routed conductor B (secondary coil). Thus, a high turn ratio monolithic transformer, using minimum die size, is...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
On-chip test circuitry which provides 8-bit-deep ECL-level patterns to 12 input pads of a 512Kb CMOS ECL SRAM at cycle times as fast as 1.4 ns has been built in a 0.8??m CMOS technology with Leff = 0.5??m. A unique approach for synchronizing the input signals to the chip-select signal in order to provide optimum set-up time and data-valid window is described. Measured results and extensive simulation...
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